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參數(shù)資料
| 型號(hào)： | SY100E195 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | Programmable Delay Chip(可編程延遲芯片) |
| 中文描述： | 可編程延時(shí)芯片（可編程延遲芯片） |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 75K |
| 代理商： | SY100E195 |
5
ClockWorks
SY10E195
SY100E195
Micrel
APPLICATIONS INFORMATION
Cascading Multiple E195s
To increase the programmable range of the E195,
internal cascade circuitry has been included. This circuitry
allows for the cascading of multiple E195s without the
need for any external gating. Furthermore, this capability
requires only one more address line per added E195.
Obviously, cascading multiple PDCs will result in a larger
programmable range; however, this increase is at the
expense of a longer minimum delay.
Figure 1 illustrates the interconnect scheme for
cascading two E195s. As can be seen, this scheme can
easily be expanded for larger E195 chains. The D
7
input
of the E195 is the cascade control pin. With the
interconnect scheme of Figure 1, when D
7
is asserted, it
signals the need for a larger programmable range than
is achievable with a single device.
An expansion of the latch section of the block diagram
is pictured below. Use of this diagram will simplify the
explanation of how the cascade circuitry works. When
D
7
of chip #1 above is low, the cascade output will also
be low, while the cascade bar output will be a logical
high. In this condition, the SET MIN pin of chip #2 will
be asserted and, thus, all of the latches of chip #2 will
be reset and the device will be set at its minimum delay.
Since the RESET and SET inputs of the latches are
overriding, any changes on the A
0
–A
6
address bus will
not affect the operation of chip #2.
Chip #1, on the other hand, will have both SET MIN
and SET MAX de-asserted so that its delay will be
controlled entirely by the address bus A
0
–A
6
. If the delay
needed is greater than can be achieved with 31.75 gate
delays (1111111 on the A
0
–A
6
address bus), D
7
will be
asserted to signal the need to cascade the delay to the
next E195 device. When D
7
is asserted, the SET MIN
pin of chip #2 will be de-asserted and the delay will be
controlled by the A
0
–A
6
address bus. Chip #1, on the
other hand, will have its SET MAX pin asserted, resulting
in the device delay to be independent of the A
0
–A
6
address bus.
When the SET MAX pin of chip #1 is asserted, the D
0
and D
1
latches will be reset while the rest of the latches
will be set. In addition, to maintain monotonicity, an
additional gate delay is selected in the cascade circuitry.
As a result, when D
7
of chip #1 is asserted, the delay
increases from 31.75 gates to 32 gates. A 32-gate delay
is the maximum delay setting for the E195.
To expand this cascading scheme to more devices,
one simply needs to connect the D
7
input and CASCADE
outputs of the current most significant E195 to the new
most significant E195 in the same manner as pictured in
Figure 1. The only addition to the logic is the increase
of one line to the address bus for cascade control of the
second PDC.
Figure 1. Cascading Interconnect Architecture
E196
Chip #1
D
4
D
5
D
6
D
7
D
2
D
3
D
1
D
0
LEN
VEE
IN
VBB
IN
S
S
C
E
C
VCC
VCCO
Q
Q
VCCO
E196
Chip #2
D
4
D
5
D
6
D
7
D
2
D
3
D
1
D
0
LEN
VEE
IN
VBB
IN
S
S
C
E
C
VCC
VCCO
Q
Q
VCCO
ADDRESS BUS (A0
–
A6)
A
7
Input
Output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY10E195 | Programmable Delay Chip(可編程延遲芯片) |
| SY10E196JCTR | PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| SY100E196 | Programmable Delay Chip with Analog Input(可編程延遲芯片（帶邏輯輸入）) |
| SY10E196 | Programmable Delay Chip with Analog Input(可編程延遲芯片（帶邏輯輸入）) |
| SY10E196JC | PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SY100E195JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:RF Micro Devices Inc 功能描述: |
| SY100E195JCTR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP |
| SY100E195JI | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100E, Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100E195JI TR | 功能描述:IC DELAY LINE 128TAP 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 延遲線 系列:100E, Precision Edge® 標(biāo)準(zhǔn)包裝:2,500 系列:- 標(biāo)片/步級(jí)數(shù):- 功能:多個(gè)，不可編程 延遲到第一抽頭:10ns 接頭增量:- 可用的總延遲:10ns 獨(dú)立延遲數(shù):4 電源電壓:4.75 V ~ 5.25 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:帶卷 (TR) |
| SY100E195JITR | 制造商:MICREL 制造商全稱:Micrel Semiconductor 功能描述:PROGRAMMABLE DELAY CHIP |
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