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參數(shù)資料
| 型號： | SY10E196JC |
| 廠商： | MICREL INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | PROGRAMMABLE DELAY CHIP WITH ANALOG INPUT |
| 中文描述： | SILICON DELAY LINE, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 79K |
| 代理商： | SY10E196JC |
DESCRIPTION
FEATURES
PROGRAMMABLE DELAY
CHIP WITH ANALOG INPUT
Rev.: E
Issue Date:
Amendment: /0
October, 1998
ClockWorks
SY10E196
SY100E196
I
Up to 2ns delay range
I
Extended 100E V
EE
range of –4.2V to –5.5V
I
≈
20ps digital step resolution
I
Linear input for tighter resolution
I
>1GHz bandwidth
I
On-chip cascade circuitry
I
75Kk
input pulldown resistor
I
Fully compatible with Motorola MC10E/100E196
I
Available in 28-pin PLCC package
The SY10/100E196 are programmable delay chips
(PDCs) designed primarily for very accurate differential
ECL input edge placement applications.
The delay section consists of a chain of gates and a
linear ramp delay adjustment organized as shown in the
logic diagram. The first two delay elements feature gates
that have been modified to have delays 1.25 and 1.5
times the basic gate delay of approximately 80ps. These
two elements provide the E196 with a digitally-selectable
resolution of approximately 20ps. The required device
delay is selected by the seven address inputs D[0:6],
which are latched on-chip by a high signal on the latch
enable (LEN) control. If the LEN signal is either LOW or
left floating, then the latch is transparent.
The FTUNE input takes an analog coltage and applies
it to an internal linear ramp for reducing the 20s resolution
still further. The FTUNE input is what differentiates the
E196 from the E195.
An eighth latched input, D7, is provided for cascading
multiple PDCs for increased programmable range. The
cascade logic allows full control of multiple PDCs, at the
expense of only a single added line to the data bus for
each additional PDC, without the need for any external
gating.
Pin
Function
IN/IN
Signal Input
EN
Input Enable
D[0:7]
Mux Select Inputs
Q/Q
Signal Output
LEN
Latch Enable
SET MIN
Minimum Delay Set
SET MAX
Maximum Delay Set
CASCADE
Cascade Signal
FTUNE
Linear Voltage Input
V
CCO
V
CC
to Output
PIN NAMES
PIN CONFIGURATION
18
17
16
15
14
13
12
5
6
7
8
9
10 11
26
27
28
1
2
3
4
TOP VIEW
PLCC
J28-1
25 24 23 22 21 20 19
D
4
D
5
D
6
D
7
D
2
D
3
N
D
1
D
0
LEN
V
EE
IN
IN
V
BB
N
N
S
S
C
E
C
FTUNE
NC
V
CC
V
CCO
Q
Q
V
CCO
1
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