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參數(shù)資料
| 型號： | STPCCONSUMER-S |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 17/51頁 |
| 文件大?。?/td> | 836K |
| 代理商： | STPCCONSUMER-S |
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PIN DESCRIPTION
17/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DACK_ENC[2:0]
DMA Acknowledge. These are
the ISA bus DMA acknowledge signals. They are
and should be decoded externally using ISACLK
and ISACLKX2 as the control strobes.
TC
ISA Terminal Count.This is the terminal count
output of the DMA controller and is connected to
the TCline of the ISA bus.It isasserted during the
last DMA transfer, when the byte count expires.
2.2.5 X-Bus Interface pins
RTCAS#
Real timeclock addressstrobe.This sig-
nal is asserted for any I/O write to port 70H.
RMRTCCS#
ROM/Real Time clock chip select.
This signal is asserted if a ROM access is decod-
ed during a memory cycle. It should be combined
with MEMR# or MEMW# signals to properly ac-
cess the ROM. During a IO cycle, this signal is as-
serted if access to the Real Time Clock (RTC) is
decoded. It should be combined with IOR or IOW#
signals to properly access the real time clock.
KBCS#
Keyboard Chip Select. This signal is as-
serted if a keyboard access is decoded during a I/
O cycle.
RTCRW#
Real Time Clock RW.This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCRW#. This signal is asserted for any
I/O write to port 71H.
RTCDS#
Real Time Clock DS This pin is a multi-
function pin. When ISAOE# is active, this signal is
used as RTCDS. This signal is asserted for any I/
O read to port 71H.
Note:
RTCDS# signals must be ORed externally with
ISAOE# and then connected to the external de-
vice. An LS244 or equivalent function can be used
if OE# is connected to ISAOE# and the output is
provided with a weak pull-up resistor as shown in
Figure 2.2.
RMRTCCS#,
KBCS#,
RTCRW#
and
2.2.6 LOCAL BUS
PA[21:0]
Address Bus Output.
PD[15:0]
Data Bus. This is the 16-bit data bus.
D[7:0] is the LSB and PD[15:8] is the MSB.
PWR#[1:0]
Write Control output.PWR0# is used
to write the LSB and PWR1# to write the MSB.
PRD#[1:0]
Read Control output. PRD0# is used
to read the LSB and PRD1# to read the MSB.
PRDY#
Data Ready input. This signal is used to
create wait states on the bus. When low, it com-
pletes the current cycle.
FCS#[1:0]
Flash Chip Select output. These are
the Programmable Chip Select signals for up to 2
banks of Flash memory.
IOCS#[3:0]
I/O Chip Select output.These are the
Programmable Chip Select signals for up to 4 ex-
ternal I/O devices.
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