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參數(shù)資料
| 型號： | STPCCONSUMER-S |
| 廠商： | 意法半導體 |
| 英文描述： | CONNECTOR ACCESSORY |
| 中文描述： | 連接器附件 |
| 文件頁數(shù)： | 15/51頁 |
| 文件大?。?/td> | 836K |
| 代理商： | STPCCONSUMER-S |
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PIN DESCRIPTION
15/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DEVSEL#
I/O Device Select. This signal is used
as an input when the STPC Consumer-S initiates
a bus cycle on the PCI bus to determine if a PCI
slave device has decoded itself to be the target of
the current transaction. It is asserted as an output
either whenthe STPC Consumer-S isthe target of
the current PCI transaction or when no other de-
vice asserts DEVSEL# prior to the subtractive de-
code phase of the current PCI transaction.
STOP#
Stop Transaction. Stop is used to imple-
ment the disconnect, retry and abort protocol of
the PCI bus. It is used as an input for the bus cy-
cles initiated by the STPC Consumer-S and is
used as an output when a PCI master cycle is tar-
geted to the STPC Consumer-S.
PAR
Parity Signal Transactions.This is the parity
signal of the PCI bus. This signal is used to guar-
antee even parity across AD[31:0], CBE#[3:0],
and PAR. This signal is driven by the master dur-
ing the address phase and data phase of write
transactions. It is driven by the target during data
phase of read transactions. (Its assertion is identi-
cal to that of theAD busdelayed by one PCI clock
cycle)
SERR#
System Error.This isthe system errorsig-
nal of the PCI bus. It may, if enabled, be asserted
for one PCI clock cycle if target aborts a STPC
Consumer-S initiated PCI transaction. Its asser-
tion byeither theSTPC Consumer-S orby another
PCI bus agent will trigger the assertion of NMI to
the host CPU. This is an open drain output.
PCIREQ#[2:0]
PCI Request. This pin are the
three external PCI master request pins. They indi-
cates to the PCI arbiter that the external agents
desire use of the bus.
PCI_GNT#[2:0]
PCI Grant. These pins indicate
that the PCI bus has been granted to the master
requesting it on its PCIREQ#.
PCI_INT[3:0]
PCI Interrupt Request. These are
the PCI bus interrupt signals.
VDD5
5V Power Supply. These power pins are
necessary for 5V ESD protection. In case the PCI
bus is used in 3.3V only, these pins can be con-
nected to 3.3V.
2.2.4 ISA INTERFACE
ISA_CLK, ISA_CLKX2
ISA Clock x1, x2. These
pins generate the Clock signal for the ISA bus and
a Doubled Clock signal. They are also used as the
multiplexor control lines for the Interrupt Controller
Interrupt input lines. ISA_CLK is generated from
either PCICLK/4 or OSC14M/ 2.
OSC14M
ISA bus synchronisation clock Output.
This is the buffered 14.318 Mhz clock for the ISA
bus.
LA[23:17]
Unlatched Address. When the ISA bus
is active, these pins are ISA Bus unlatched ad-
dress for 16-bit devices. When ISA bus is ac-
cessed by any cycle initiated from PCI bus, these
pins are in output mode. When an ISA bus master
owns the bus, these pins are in input mode.
SA[19:0]
ISA Address Bus. System address bus
of ISA on 8-bit slot. These pins are used as an in-
put when anISA bus master owns the busand are
outputs at all other times.
SD[15:0]
I/O Data Bus. These pins are the exter-
nal databus to the ISA bus.
ALE
Address Latch Enable. This is the address
latch enable output of the ISA bus and is asserted
by the STPC Consumer-S to indicate that LA23-
17, SA19-0, AEN and SBHE# signals are valid.
The ALE is driven high during refresh, DMA mas-
ter or an ISA master cycles by the STPC Consum-
er-S. ALE is driven low after reset.
MEMR#
Memory Read. This is the memory read
command signal of the ISAbus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
The MEMR# signal is active during refresh.
MEMW#
Memory Write. This is the memory write
command signal of the ISAbus. It is used as an in-
put when an ISA master owns the bus and is an
output at all other times.
SMEMR#
System Memory Read.The STPC Con-
sumer-S generates SMEMR# signal of the ISA
bus only whenthe addressis below one megabyte
or the cycle is a refresh cycle.
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