參數(shù)資料
型號(hào)： STMPE2401TBR
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 24 I/O, PIA-GENERAL PURPOSE, PBGA36
封裝： LEAD FREE, TFBGA-36
文件頁數(shù)： 15/55頁
文件大?。?/td> 959K
代理商： STMPE2401TBR
Interrupt system
STMPE2401
22/55
9
Interrupt system
STMPE2401 uses a highly flexible interrupt system. It allows host system to configure the
type of system events that should result in an interrupt, and pinpoints the source of interrupt
by status register. The INT pin could be configured as ACTIVE HIGH, or ACTIVE LOW.
32KHz clock input or crystal must be available for the interrupt system to be functional.
INT pin is 3.3V tolernat.
Once asserted, the INT pin would de-assert only if the corresponding bit in the
InterruptStatus register is cleared.
Figure 7.
Interrupt system
9.1
Register map of interrupt system
Table 20. Register map of interrupt system
Address
Register Name
Description
Auto-Increment
(during sequential R/W)
0x10
ICR_msb
Interrupt Control Register
Yes
0x11
ICR_lsb
Yes
0x12
IER_msb
Interrupt Enable Mask Register
Yes
0x13
IER_lsb
Yes
0x14
ISR_msb
Interrupt Status Register
Yes
0x15
ISR_lsb
Yes
0x16
IEGPIOR_msb
Interrupt Enable GPIO Mask
Register
Yes
0x17
IEGPIOR_mid
Yes
0x18
IEGPIOR_lsb
Yes
0x19
IEGPIOR_msb
Interrupt Status GPIO Register
Yes
0x1A
ISGPIOR_mid
Yes
0x1B
ISGPIOR_lsb
Yes
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