參數(shù)資料
型號(hào)： STM32F103RCH7XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
封裝： ROHS COMPLIANT, LFBGA-64
文件頁(yè)數(shù)： 99/115頁(yè)
文件大?。?/td> 1225K
代理商： STM32F103RCH7XXX
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
5.3.16
Communications interfaces
I
2C interface characteristics
Unless otherwise specified, the parameters given in Table 50 are derived from tests
performed under ambient temperature, fPCLK1 frequency and VDD supply voltage conditions
summarized in Table 10.
The STM32F103xC performance line I
2C interface meets the requirements of the standard
I
2C communication protocol with the following restrictions: the I/O pins SDA and SCL are
mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected
between the I/O pin and VDD is disabled, but is still present.
The I
2C characteristics are described in Table 50. Refer also to Section 5.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 50.
I2C characteristics
Symbol
Parameter
Standard mode I2C(1)
1.
Guaranteed by design, not tested in production.
Fast mode I2C(1)(2)
2.
fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I
2C frequency. It must be
higher than 4 MHz to achieve the maximum fast mode I2C frequency.
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
1.3
s
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
ns
th(SDA)
SDA data hold time
0(3)
3.
The maximum hold time of the Start condition has only to be met if the interface does not stretch the low
period of SCL signal.
0(4)
4.
The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
20 + 0.1Cb
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
Start condition hold time
4.0
0.6
s
tsu(STA)
Repeated Start condition
setup time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
1.3
μs
Cb
Capacitive load for each bus
line
400
pF
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