參數(shù)資料
型號(hào)： STM32F103RCH7XXX
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA64
封裝： ROHS COMPLIANT, LFBGA-64
文件頁數(shù)： 88/115頁
文件大?。?/td> 1225K
代理商： STM32F103RCH7XXX
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
NAND controller waveforms and timings
Figure 36 through Figure 39 respresent synchronous waveforms and Table 40 provides the
corresponding timings. The results shown in this table are obtained with the following FSMC
configuration:
●
COM.FSMC_SetupTime = 0x01;
●
COM.FSMC_WaitSetupTime = 0x03;
●
COM.FSMC_HoldSetupTime = 0x02;
●
COM.FSMC_HiZSetupTime = 0x01;
●
ATT.FSMC_SetupTime = 0x01;
●
ATT.FSMC_WaitSetupTime = 0x03;
●
ATT.FSMC_HoldSetupTime = 0x02;
●
ATT.FSMC_HiZSetupTime = 0x01;
●
Bank = FSMC_Bank_NAND;
●
MemoryDataWidth = FSMC_MemoryDataWidth_16b;
●
ECC = FSMC_ECC_Enable;
●
ECCPageSize = FSMC_ECCPageSize_512Bytes;
●
TCLRSetupTime = 0;
●
TARSetupTime = 0;
tw(NIOWR)
FSMC_NIOWR low width
8THCLK + 3
ns
tv(NIOWR-D)
FSMC_NIOWR low to FSMC_D[15:0] valid
5THCLK +1
ns
th(NIOWR-D)
FSMC_NIOWR high to FSMC_D[15:0] invalid
11THCLK
ns
td(NCE4_1-NIOWR) FSMC_NCE4_1 low to FSMC_NIOWR valid
5THCLK+3ns
ns
th(NCEx-NIOWR)
th(NCE4_1-NIOWR)
FSMC_NCEx high to FSMC_NIOWR invalid
FSMC_NCE4_1 high to FSMC_NIOWR invalid
5THCLK – 5
ns
td(NIORD-NCEx)
td(NIORD-NCE4_1)
FSMC_NCEx low to FSMC_NIORD valid FSMC_NCE4_1
low to FSMC_NIORD valid
5THCLK + 2.5 ns
th(NCEx-NIORD)
th(NCE4_1-NIORD)
FSMC_NCEx high to FSMC_NIORD invalid
FSMC_NCE4_1 high to FSMC_NIORD invalid
5THCLK – 5
ns
tsu(D-NIORD)
FSMC_D[15:0] valid before FSMC_NIORD high
4.5
ns
td(NIORD-D)
FSMC_D[15:0] valid after FSMC_NIORD high
9
ns
tw(NIORD)
FSMC_NIORD low width
8THCLK + 2
ns
1.
VDD_IO = V and CL = 15 pF.
2.
Based on characterization, not tested in production.
Table 39.
Switching characteristics for PC Card/CF read and write cycles(1)(2) (continued)
Symbol
Parameter
Min
Max
Unit
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