參數(shù)資料
型號(hào): ST7LITE19F1B6
英文描述: FUSE CLIP 3AG SLDR LUG TIN BRASS
中文描述: ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時(shí)器。的SPI
文件頁(yè)數(shù): 26/122頁(yè)
文件大?。?/td> 1716K
代理商: ST7LITE19F1B6
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ST7LITE0, ST7SUPERLITE
26/122
1
7.4 RESET SEQUENCE MANAGER (RSM)
7.4.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
Figure 15
:
I
External RESET source pulse
I
Internal LVD RESET (Low Voltage Detection)
I
Internal WATCHDOG RESET
These sources act on the RESET pin and it is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of 3 phases
as shown in
Figure 14
:
I
Active Phase depending on the RESET source
I
256 CPU clock cycle delay
I
RESET vector fetch
The 256 CPU clock cycle delay allows the oscilla-
tor to stabilise and ensures that recovery has tak-
en place from the Reset state.
The RESET vector fetch phase duration is 2 clock
cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
STARTUP
(see
Figure 12
).
Figure 14. RESET Sequence Phases
Figure 15. Reset Block Diagram
RESET
Active Phase
INTERNAL RESET
256 CLOCK CYCLES
FETCH
VECTOR
RESET
R
ON
V
DD
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
PULSE
GENERATOR
FILTER
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