參數(shù)資料
型號(hào): ST7LITE15F1B6
英文描述: CLIP FUSE 10A 5X20MM PC MOUNT
中文描述: ST7LITE1 - 8單電壓閃存EEPROM的MEMORY.DATA位MCU。 ADC的。 4定時(shí)器。的SPI
文件頁(yè)數(shù): 18/122頁(yè)
文件大?。?/td> 1716K
代理商: ST7LITE15F1B6
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ST7LITE0, ST7SUPERLITE
18/122
1
DATA EEPROM
(Cont’d)
5.4 POWER SAVING MODES
Wait mode
The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler or when the microcontroller enters Active-HALT
mode.The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.
Active-Halt mode
Refer to Wait mode.
Halt mode
The DATA EEPROM immediately enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.
5.5 ACCESS ERROR HANDLING
If a read access occurs while E2LAT=1, then the
data bus will not be driven.
If a write access occurs while E2LAT=0, then the
data on the bus will not be latched.
If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.
5.6 Data EEPROM Read-out Protection
The read-out protection is enabled through an op-
tion bit (see
section 15.1 on page 109
).
When this option is selected, the programs and
data stored in the EEPROM memory are protected
against read-out piracy (including a re-write pro-
tection). In Flash devices, when this protection is
removed by reprogramming the Option Byte, the
entire Program memeory and EEPROM is first au-
tomatically erased.
Note:
Both Program Memory and data EEPROM
are protected using the same option bit.
Figure 9. Data EEPROM Programming Cycle
LAT
ERASE CYCLE
WRITE CYCLE
PGM
t
PROG
READ OPERATION NOT POSSIBLE
WRITE OF
DATA LATCHES
READ OPERATION POSSIBLE
INTERNAL
PROGRAMMING
VOLTAGE
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