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參數(shù)資料
| 型號： | ST72T121J2B6 |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 中文描述： | 8位微控制器與2/4/8K字節(jié)在系統(tǒng)可編程閃存 |
| 文件頁數(shù)： | 39/93頁 |
| 文件大小： | 915K |
| 代理商： | ST72T121J2B6 |
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ST72E121 ST72T121
16-BIT TIMER
(Cont’d)
5.3.3.4 Output Compare
In this section, the index,
i
, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
i
R value to 8000h.
Timing resolution is one count of the free running
counter: (
f
CPU/
CC[1:0]
).
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC
i
E bit if an output is needed then the
OCMP
i
pin is dedicated to the output compare
i
signal.
– Select the timer clock (CC[1:0]) (see
Table 14
).
And select the following in the CR1 register:
– Select the OLVL
i
bit to applied to the OCMP
i
pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCF
i
bit is set.
– The OCMP
i
pin takes OLVL
i
bit value (OCMP
i
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see
Table 14
)
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
If the timer clock is an external clock, the formula
is:
OC
i
R =
t
*
f
EXT
Where:
t
f
EXT
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCF
i
bit) is done by:
1. Reading the SR register while the OCF
i
bit is
set.
2. An access (read or write) to the OC
i
LR register.
The following procedure is recommended to pre-
vent the OCF
i
bit from being set between the time
it is read and the write to the OC
i
R
register:
– Write to the OC
i
HR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCF
i
bit, which may be already set).
– Write to the OC
i
LR register (enables the output
compare function and clears the OCF
i
bit).
MS Byte
OCiHR
LS Byte
OCiLR
OCiR
OC
i
R =
t
*
f
CPU
PRESC
39
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST72T121J2T6 | 功能描述:8位微控制器 -MCU OTP EPROM 8K SPI/SCI RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T121J2T6S | 制造商:STMicroelectronics 功能描述: |
| ST72T121J4B6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI/SC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T121J4T6 | 功能描述:8位微控制器 -MCU OTP EPROM 16K SPI/SC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| ST72T121J4T6S | 制造商:STMicroelectronics 功能描述: |
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