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| 型號(hào)： | ST72521BR9 |
| 英文描述： | ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE |
| 中文描述： | ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個(gè)定時(shí)器。的SPI。脊髓損傷。 I2C總線(xiàn)。 CAN接口 |
| 文件頁(yè)數(shù)： | 30/198頁(yè) |
| 文件大?。?/td> | 2504K |
| 代理商： | ST72521BR9 |
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ST72521B
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6 INTERRUPTS
6.1 INTRODUCTION
The ST7 enhanced interrupt management pro-
vides the following features:
I
Hardware interrupts
I
Software interrupt (TRAP)
I
Nested or concurrent interrupt management
with flexible interrupt priority and level
management:
– Up to 4 software programmable nesting levels
– Up to 16 interrupt vectors fixed by hardware
– 2 non maskable events: RESET, TRAP
– 1 maskable Top Level event: TLI
This interrupt management is based on:
– Bit 5 and bit 3 of the CPU CC register (I1:0),
– Interrupt software priority registers (ISPRx),
– Fixed interrupt vector addresses located at the
high addresses of the memory map (FFE0h to
FFFFh) sorted by hardware priority order.
This enhanced interrupt controller guarantees full
upward compatibility with the standard (not nest-
ed) ST7 interrupt controller.
6.2 MASKING AND PROCESSING FLOW
The interrupt masking is managed by the I1 and I0
bits of the CC register and the ISPRx registers
which give the interrupt software priority level of
each interrupt vector (see
Table 4
). The process-
ing flow is shown in
Figure 16
When an interrupt request has to be serviced:
– Normal processing is suspended at the end of
the current instruction execution.
– The PC, X, A and CC registers are saved onto
the stack.
– I1 and I0 bits of CC register are set according to
the corresponding values in the ISPRx registers
of the serviced interrupt vector.
– The PC is then loaded with the interrupt vector of
the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
“Interrupt Mapping” table for vector addresses).
The interrupt service routine should end with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.
Note
: As a consequence of the IRET instruction,
the I1 and I0 bits will be restored from the stack
and the program in the previous level will resume.
Table 4. Interrupt Software Priority Levels
Interrupt software priority
Level 0 (main)
Level 1
Level 2
Level 3 (= interrupt disable)
Figure 16. Interrupt Processing Flowchart
Level
Low
I1
1
0
0
1
I0
0
1
0
1
High
“IRET”
RESTORE PC, X, A, CC
FROM STACK
STACK PC, X, A, CC
LOAD I1:0 FROM INTERRUPT SW REG.
LOAD PC FROM INTERRUPT VECTOR
FETCH NEXT
INSTRUCTION
RESET
TRAP
PENDING
INTERRUPT
I1:0
Y
N
Y
N
Y
N
Interrupt has the same or a
lower software priority
than current one
THE INTERRUPT
STAYS PENDING
I
s
t
EXECUTE
INSTRUCTION
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