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參數(shù)資料
| 型號(hào)： | ST72521BR9 |
| 英文描述： | ST72521B - 80/64-PIN 8-BIT MCU WITH 32 TO 60K ROM. FIVE TIMERS. SPI. SCI. I2C. CAN INTERFACE |
| 中文描述： | ST72521B - 80/64-PIN 8位32至60,000 ROM的微處理器。 5個(gè)定時(shí)器。的SPI。脊髓損傷。 I2C總線。 CAN接口 |
| 文件頁數(shù)： | 104/198頁 |
| 文件大?。?/td> | 2504K |
| 代理商： | ST72521BR9 |
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ST72521B
104/198
SERIAL COMMUNICATIONS INTERFACE
(Cont’d)
9.6.4.7 Parity Control
Parity control (generation of parity bit in trasmis-
sion and and parity chencking in reception) can be
enabled by setting the PCE bit in the SCICR1 reg-
ister. Depending on the frame length defined by
the M bit, the possible SCI frame formats are as
listed in
Table 19
.
Table 19. Frame Formats
Legend:
SB = Start Bit, STB = Stop Bit,
PB = Parity Bit
Note
: In case of wake up by an address mark, the
MSB bit of the data is taken into account and not
the parity bit
Even parity:
the parity bit is calculated to obtain
an even number of “1s” inside the frame made of
the 7 or 8 LSB bits (depending on whether M is
equal to 0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
0 if even parity is selected (PS bit = 0).
Odd parity:
the parity bit is calculated to obtain an
odd number of “1s” inside the frame made of the 7
or 8 LSB bits (depending on whether M is equal to
0 or 1) and the parity bit.
Ex: data=00110101; 4 bits set => parity bit will be
1 if odd parity is selected (PS bit = 1).
Transmission mode:
If the PCE bit is set then the
MSB bit of the data written in the data register is
not transmitted but is changed by the parity bit.
Reception mode:
If the PCE bit is set then the in-
terface checks if the received data byte has an
even number of “1s” if even parity is selected
(PS=0) or an odd number of “1s” if odd parity is se-
lected (PS=1). If the parity check fails, the PE flag
is set in the SCISR register and an interrupt is gen-
erated if PIE is set in the SCICR1 register.
9.6.4.8 SCI Clock Tolerance
During reception, each bit is oversampled 16
times. The mean of the 8
th
, 9
th
and 10
th
samples is
considered as the bit value.
Consequently, the clock frequency should not vary
more than 6/16 (37.5%) within one bit.
The sampling clock is resynchronized at each start
bit, so that when receiving 10 bits (one start bit, 1
data byte, 1 stop bit), the clock deviation should
not exceed 3.75%.
9.6.4.9 Clock Deviation Causes
The causes which contribute to the total deviation
are:
– D
TRA
: Deviation due to transmitter error (Local
oscillator error of the transmitter or the trans-
mitter is transmitting at a different baud rate).
– D
QUANT
: Error due to the baud rate quantisa-
tion of the receiver.
– D
REC
: Deviation of the local oscillator of the
receiver: This deviation can occur during the
reception of one complete SCI message as-
suming that the deviation has been compen-
sated at the beginning of the message.
– D
TCL
: Deviation due to the transmission line
(generally due to the transceivers)
All the deviations of the system should be added
and compared to the SCI clock tolerance:
D
TRA
+ D
QUANT
+ D
REC
+ D
TCL
< 3.75%
Figure 61. Bit Sampling in Reception Mode
M bit
0
0
1
1
PCE bit
0
1
0
1
SCI frame
| SB | 8 bit data | STB |
| SB | 7-bit data | PB | STB |
| SB | 9-bit data | STB |
| SB | 8-bit data PB | STB |
RDI LINE
Sample
clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
sampled values
One bit time
6/16
7/16
7/16
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