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參數(shù)資料
| 型號： | ST6382B1/XXX |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, MICROCONTROLLER, PDIP42 |
| 封裝： | PLASTIC, SDIP-42 |
| 文件頁數(shù)： | 5/82頁 |
| 文件大小： | 1651K |
| 代理商： | ST6382B1/XXX |
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Obsolete
Product(s)
- Obsolete
Product(s)
13/82
ST6388, ST63E88, ST63T88
MEMORY SPACES (Cont’d)
1.3.4
Data
RAM/EEPROM/OSD
RAM
Addressing
In all members of the ST638x family 64 bytes of
data RAM are directly addressable in the data
space from 80h to BFh addresses. The additional
192 bytes of RAM, the 384 bytes of EEPROM, and
the OSD RAM can be addressed using the banks
of 64 bytes located between addresses 00h and
3Fh. The selection of the bank is done by pro-
gramming the Data RAM Bank Register (DRBR)
located at the E8h address of the Data Space. In
this way each bank of RAM, EEPROM or OSD
RAM can select 64 bytes at a time. No more than
one bank should be set at a time.
Data RAM Bank Register (DRBR)
Address: E8h - Write only
Reset Value: XXh
DRBR7,DRBR1,DRBR0. These bits select the
EEPROM pages.
DRBR6, DRBR5. Each of these bits, when set, will
select one OSD RAM register page.
DRBR4,DRBR3,DRBR2. Each of these bits, when
set, will select one RAM page.
This register is undefined after reset.
Table 5 summarizes how to set the Data RAM
Bank Register in order to select the various banks
or pages.
Caution: This register contains at least one write
only bit. Single bit instructions (SET, RES, INC
and DEC) should not be used.
Note: Care is required when handling the DRBR
as it is write only. For this reason, it is not allowed
to change the DRBR contents while executing in-
terrupts drivers, as the driver cannot save and
than restore its previous content. If it is impossible
to avoid the writing of this register in interrupts
drivers, an image of this register must be saved in
a RAM location, and each time the program writes
the DRBR it writes also the image register. The im-
age register must be written first, so if an interrupt
occurs between the two instructions the DRBR is
not affected.
Table 5. Data RAM Bank Register Set-up
70
DRBR
7
DRBR
6
DRBR
5
DRBR
4
DRBR
3
DRBR
2
DRBR
1
DRBR
0
DRBR Value
Selection
Hex.
Binary
01h
0000 0001
EEPROM Page 0
02h
0000 0010
EEPROM Page 1
03h
0000 0011
EEPROM Page 2
81h
1000 0001
EEPROM Page 3
82h
1000 0010
EEPROM Page 4
83h
1000 0011
EEPROM Page 5
04h
0000 0100
RAM Page 2
08h
0000 1000
RAM Page 3
10h
0001 0000
RAM Page 4
20h
0010 0000
OSD Page 5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST6386B1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST6388B1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST6387B1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST6394B1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
| ST6399B1 | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST6382B4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6383 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6383B1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6383B4 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
| ST6385 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-BIT MCUs WITH ON-SCREEN-DISPLAY FOR TV TUNING |
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