- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299943 > ST52513G3 MAX 7000 CPLD 512 MC 256-FBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | ST52513G3 |
| 英文描述： | MAX 7000 CPLD 512 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護(hù)病房，10位ADC。兩個(gè)定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 64/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513G3 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁當(dāng)前第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁
9 INSTRUCTION SET
ST52F501L/F502L supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F501L/F502L can perform
multiplication
(MULT)
and
division
(DIV).
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 3.4).
9.1 Addressing Modes
ST52F501L/F502L instructions allow the following
addressing modes:
s
Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
instruction. Examples: NOP, SCF.
s
Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
s
Direct: the operands of these instructions are
specified with the direct addresses. The
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
s
Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
s
Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
9.2 Instruction Types
ST52F501L/F502L
supplies
the
following
instruction types:
s
Load Instructions
s
Arithmetic and Logic Instructions
s
Bitwise instructions
s
Jump Instructions
s
Interrupt Management Instructions
s
Control Instructions
The instructions are listed in Table 9.1
Table 9.1 Instruction Set
Load Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
BLKSET
BLKSET const
2
(*)
-
GETPG
GETPG regx
2
7
-
LDCE
LDCE confx,memy
3
8/9
-
LDCI
LDCI confx, const
3
7
-
LDCNF
LDCNF regx, conf
3
7
-
LDCR
LDCR confx, regy
3
8
-
LDER
LDER memx, regy
3
10
-
LDER
LDER (regx),(regy)
3
11
-
LDER
LDER (regx), regy
3
10
-
LDER
LDER memx,(regy)
3
11
-
LDFR
LDFR fuzzyx, regy
3
8
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52513K2 | MAX 3000A CPLD 32 MC 44-PLCC |
| ST52513K3 | MAX 3000A CPLD 64 MC 100-TQFP |
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513K2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。