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| 型號： | ST52513G3 |
| 英文描述： | MAX 7000 CPLD 512 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數(shù)： | 18/106頁 |
| 文件大小： | 1355K |
| 代理商： | ST52513G3 |
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When a return occurs (RET or RETI instruction),
the SSP is increased by 2 and the data stored in
the pointed locations couple is restored back into
the PC.
The current SSP can be read and write in the
couple of Configuration Registers 44 02Ch (MSB:
page number, always 32 020h) and 45 02Dh (LSB:
location address) (see Figure 2.3). In ST52F501L/
F502L the user can only consider the LSB because
the MSB is always the same.
The User Stack is used to store user data and is
located beginning from a RAM bench location set
by the user (USTP) by writing the couple of
Configuration Registers 5 005h (MSB: page
number) and 6 005h (LSB: location address) (see
Figure 2.3). Register 5, which is the page number,
must always be set to a value between 32 (020h)
and 255 (0FFh): values higher than 32 always
address RAM on page 32.
This feature allows a flexible use of the User Stack
in terms of dimension and to avoid overlaps. The
User Stack Pointer (USP) points to the first
currently available stack location. When the user
stores a byte value contained in the Register File
by using the PUSH instruction, the value is stored
in the position pointed to by the USP that is
increased (the User Stack order is opposite to the
System Stack one). When the user takes a value
from the User Stack with the POP instruction, the
USP is decreased and the value pointed to is
copied in the specified Register File location.
By writing the USTP, the new address is
automatically written in the USP. The current USP
can be read from the Input Registers 11 0Bh (MSB:
page number, always 32 020h) and 12 0Ch (LSB:
location address) (see Figure 2.3). In ST52F501L/
F502L the user can only consider the LSB because
the MSB is always the same.
Note: The user must pay close attention to avoid
overlapping user and Stacks data. The User Stack
Top location and the System Stack Pointer should
be configured with care in order to have enough
space between the two stacks.
2.5 Input Registers
The ST52F501L/F502L Input Registers bench
consists of a file of 8-bit registers containing data
or the status of the peripherals. For example, the
Input Registers contain data converted by the
ADC, Ports, serial communication peripherals,
Timers, etc.
The Input Registers can be accessed by using the
LDRI instruction that loads the specified Register
File address with the contents of the specified
Input Register. See the Programming Manual for
further details on this instruction. The Input
Registers are read-only registers.
In order to simplify the concept, a mnemonic name
is assigned to each register. The list of the Input
Registers is shown in Table 2.1.
2.6 Output registers
The ST52F501L/F502L Output Registers bench
consists of a file of 8-bit registers containing data
sent to the Peripherals and the I/O Ports (for
example: Timer Counters, data to be transmitted
by the serial communication peripherals, data to be
sent to the Port pins in output, etc.).
The registers are located inside the Peripherals
and Ports, which allow flexibility and modularity in
the design of new family devices.
The Output Registers are write only. In order to
access the configuration Register the user can use
the following instructions:
s
LDPI: loads the immediate value in the specified
Output Register.
s
LDPR: loads the contents of the specified
Register File location into the output register
specified. This instruction allows computed data
to be sent to Peripherals and Ports.
s
LDPE direct: loads the contents of the specified
Program/Data Memory location into the output
register specified. This instruction allows data to
be sent to Peripherals and Ports from a table.
s
LDPE indirect: loads the contents of the
Program/Data Memory location whose address
is contained in the specified Register File
location into the output register specified. This
instruction allows data to be sent to Peripherals
and Ports from a table pointed to by a register.
See the Programming manual for further details
about these instructions.
In order to simplify the concept, a mnemonic name
is assigned to each register. The list of the Output
Registers is shown in Table 2.2.
2.7 Configuration Registers & Option Bytes
The ST52F501L/F502L Configuration Registers
bench consists of a file of 8-bit registers that allows
the configuration of all the ICU blocks. The
registers are located inside the block they
configure in order to obtain greater flexibility and
modularity in the design of new family devices. In
the Configuration Registers, each bit has a
peculiar use, so the logic level of each of them
must be considered.
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| ST52513K2 | MAX 3000A CPLD 32 MC 44-PLCC |
| ST52513K3 | MAX 3000A CPLD 64 MC 100-TQFP |
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52513K2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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