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參數資料
| 型號： | ST52513G3 |
| 英文描述： | MAX 7000 CPLD 512 MC 256-FBGA |
| 中文描述： | 8位重癥監(jiān)護病房，10位ADC。兩個定時器/脈寬調制。 I2C總線。的SPI。脊髓損傷。提供了8K閃存 |
| 文件頁數： | 17/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52513G3 |
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Flash and EEPROM are programmed electrically
just applying the supply voltage and it is also
erased electrically; this feature allows the user to
easily reprogram the memory without taking the
device off from the board (In Situ Programming
ISP). Data and commands are transmitted through
the I2C serial communication protocol. Data can
also be written run-time with the In Application
Programming (IAP)
NVM can be locked by the user during the
programming phase, in order to prevent external
operation such as reading the program code and
assuring protection of user intellectual property.
Flash and EEPROM pages can be protected by
unintentional writings.
The operations that can be performed on the NVM
during the Programming Phase, ISP and IAP are
described in detail in the Section 4.
Figure 2.3 System and User Stack
2.4 System and User Stacks
The System and User Stacks are located in the
Program/Data memory in the RAM benches.
System Stacks are used to push the Program
Counter (PC) after an Interrupt Request or a
Subroutine Call. After a RET (Return from a
subroutine) or a RETI (Return from an interrupt)
the PC that is saved is popped from the stack and
restored. After an interrupt request, the flags are
also saved in a reserved stack inside the core, so
each interrupt has its own flags.
The System Stack is located in the last RAM bench
starting from the last address (255) inside the
bench page. The System Stack Pointer (SSP) can
be read and modified by the user. For each level of
stack 2 bytes of the RAM are used. The SSP points
to the first currently available stack position. When
a subroutine call or interrupt request occurs, the
content of the PC is stored in a couple of locations
pointed to by the SSP that is decreased by 2.
20FFh
2000h
2001h
20FEh
REGISTER FILE
CONFIGURATION REGISTERS
USER STACK TOP MSB
USER STACK TOP LSB
PROGRAM COUNTER
RAM BENCH
SYSTEM STACK
POINTER
USER STACK
POINTER
USER DATA
PAGE NUMBER
LOCATION ADRESS
IRQ
RETI
POP X
PUSH X
REGISTER X
LSB
MSB
SYSTEM STACK
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
USER STACK LEVEL 1
USER STACK LEVEL 2
USER STACK LEVEL 3
USER STACK LEVEL 4
相關PDF資料 |
PDF描述 |
|---|---|
| ST52513K2 | MAX 3000A CPLD 32 MC 44-PLCC |
| ST52513K3 | MAX 3000A CPLD 64 MC 100-TQFP |
| ST52513Y2 | MAX 3000A CPLD 256 MC 256-FBGA |
| ST52513Y3 | MAX II CPLD 570 LE 256-FBGA |
| ST52514F1 | MAX II CPLD 570 LE 100-TQFP |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ST52513K2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513K3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52513Y3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
| ST52514F1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH 10-BIT ADC. TWO TIMERS/PWM. I2C. SPI. SCI. UP TO 8K FLASH |
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