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參數(shù)資料
| 型號(hào)： | ST52501LF3 |
| 英文描述： | MAX 7000 CPLD 128 MC 100-PQFP |
| 中文描述： | 8位紅外驅(qū)動(dòng)重癥監(jiān)護(hù)病房。定時(shí)器/脈寬調(diào)制。 I2C總線。的SPI。脊髓損傷。低電壓 |
| 文件頁數(shù)： | 103/106頁 |
| 文件大?。?/td> | 1355K |
| 代理商： | ST52501LF3 |
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Figure 14.2 Serial Peripheral Interface Block Diagram
Procedure
– Select the SPR0, SPR1 and SPR2 bits to define
the serial clock baud rate (see SPI_CR register).
– Select the CPOL and CPHA bits to define one of
the four relationships between the data transfer
and the serial clock (see Figure 14.4).
–The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a high
level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
The data byte is loaded in parallel into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set
2. A read to the SPI_IN register.
Note: While the SPIF bit is set, all writes to the
SPI_OUT
register
are
inhibited
until
the
SPI_STATUS_CR register is read.
SPI_IN
Read Buffer
8-Bit Shift Register
Write
Read
Internal Bus
SPI
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SPIF WCOL
MODF
SERIAL
CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
STATE
SPI_CR
SPI_STATUS_CR
-
IT
request
MASTER
CONTROL
SPR2
OR
SSI
SSM
SOD
SPI_OUT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ST52501LG1 | MAX 7000 CPLD 128 MC 160-PQFP |
| ST52501LG2 | MAX 7000 CPLD 128 MC 100-TQFP |
| ST52501LG3 | MAX 7000 CPLD 128 MC 100-TQFP |
| ST52501LK1 | MAX 7000 CPLD 160 MC 84-PLCC |
| ST52501LK2 | MAX 7000 CPLD 160 MC 100-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ST52501LG1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LG2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LG3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LK1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
| ST52501LK2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-BIT ICU WITH IR DRIVER. TIMER/PWM. I2C. SPI. SCI. LOW VOLTAGE |
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