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參數(shù)資料
| 型號(hào)： | ST52440G2 |
| 英文描述： | MAX 7000 CPLD 64 MC 44-TQFP |
| 中文描述： | 8位重癥監(jiān)護(hù)病房與定時(shí)器/脈寬調(diào)制。模擬比較器。可控硅/ PWM定時(shí)器。水分散粒劑。提供了8K存儲(chǔ)器 |
| 文件頁數(shù)： | 18/88頁 |
| 文件大?。?/td> | 1162K |
| 代理商： | ST52440G2 |
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ST52T430/E430
25/88
PHASE and RST_ADD signals are active low,
RST_CONF signal is active high.
Port A is used for the memory data I/O.
(See Table
3.2 for pin reference on the different packages).
Memory may be locked by means of the Memory
Lock Status, which is a flag used to enable
EPROM operations.
If Memory Lock Status is 1 all EPROM operations
are enabled, otherwise the user may only read
(and verify) the OTP code and the Memory Lock
Status.
Only if EPROM is not locked by means of Lock Cell
(see EPROM Locking may EPROM operations be
enabled by changing the Memory Lock Status from
0 to 1.
RST_ADD signal resets the memory address
register and the Memory Lock Status. When the
RST_ADD becomes high, the memory must be
unlocked in order to read or write.
INC_ADD signal increments the memory address.
RST_CONF signal resets the EPROM Control
Register. When RST_CONF is high, the DATA I/
O Port A is in output, otherwise it is always in
input.
INC_CONF signal increments the EPROM Control
Register value.
PHASE signal validates the operation selected by
means of the EPROM Control Register value.
3.1.1 EPROM Operation.
In order to execute an EPROM operation (See
Table 3.2), the corresponding identification value
must be loaded in the EPROM Control Register.
The signal timing is the following: RST_ADD= high
and PHASE= high, RST_CONF changes from low
to high level, to reset the EPROM Control Register,
and INC_CONF signal generates a number of
positive pulses equal to the value to be loaded.
After this sequence, a negative pulse of the
PHASE signal will validate the operation selected.
The minimum PHASE signal pulse width must be
10
s for EPROM Writing Operation and 100 ns for
the others.
When RST_CONF is high, DATA I/O Port A is
enabled
in
output
and
the
reading/verifying
operation results are available.
After a writing operation, when RST_CONF is high,
Port A is in output without valid data.
3.1.2 EPROM Locking.
The Memory Lock operation, which is identified
with the number 4 in the EPROM Control Register,
writes “0" in the Memory Lock Cell.
At the beginning of an External Operation, when
the RST_ADD signal changes from low level to
high level, the Memory Lock Status is “0", therefore
it must be unlocked before proceeding.
In order to unlock the Memory Lock Status the
operation, which is identified by the number 2 in
the EPROM Control Register must be executed
(see Figure 3.2).
Memory Lock Status can be changed only if
Memory Lock Cell is “1". After a Memory Lock
operation external operations cannot be executed
except to read (or verify) the OTP Code and the
Memory Lock Status.
3.1.3 EPROM Writing.
When the memory is blank, all bits are at logic level
“1". Data is introduced by programming only the
zeros in the desired memory location. However, all
input data must contain both ”1" and “0".
The only way to change “0" into ”1" is to erase the
entire memory (by exposure to Ultra Violet light)
and reprogram it.
The memory is in Writing mode when the EPROM
Control Register value is 3.
The VPP voltage must be 12V±5%, with stable data
on the data bus PA(0:7).
The timing signals are the following (see Figure ):
1) RST_ADD and RST_CONF change from low to
high level,
2) two pulses on INC_CONF signal load the
Memory Unlock operation code,
3) a negative pulse (100 ns) on the PHASE signal
validates the Memory Unlock operation,
4) a negative pulse on RST_CONF signal resets
the EPROM Control Register,
5) three positive pulses on INC_CONF load the
Memory Writing operation code,
6) a train of positive pulses on INC_ADD signal
increments the memory location address up to the
requested value (generally this is a sequential
operation and only one pulse is used),
7) a negative pulse (10
s) on the PHASE signal
validates the Memory Writing operation.
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