參數(shù)資料
型號(hào)： ST16C654IQ64
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
中文描述： 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁(yè)數(shù)： 51/51頁(yè)
文件大小： 968K
代理商： ST16C654IQ64
ST16C654/654D
REV. 5.0.0
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
II
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 27
T
ABLE
11: I
NTERRUPT
S
OURCE
AND
P
RIORITY
L
EVEL
..................................................................................................................... 27
T
ABLE
12: T
RANSMIT
AND
R
ECEIVE
FIFO T
RIGGER
L
EVEL
S
ELECTION
............................................................................................ 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 30
T
ABLE
13: P
ARITY
SELECTION
........................................................................................................................................................ 30
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 31
T
ABLE
14: INT O
UTPUT
M
ODES
..................................................................................................................................................... 31
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 32
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 33
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 33
4.12 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 33
T
ABLE
15: S
OFTWARE
F
LOW
C
ONTROL
F
UNCTIONS
........................................................................................................................ 34
4.13 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 35
4.14 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 35
T
ABLE
16: UART RESET CONDITIONS FOR CHANNELS A-D.................................................................................................. 36
ABSOLUTE MAXIMUM RATINGS...................................................................................37
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)37
ELECTRICAL CHARACTERISTICS ................................................................................37
DC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................37
AC E
LECTRICAL
C
HARACTERISTICS
..............................................................................................................38
TA=0
O
TO
70
O
C (-40
O
TO
+85
O
C
FOR
INDUSTRIAL
GRADE
PACKAGE
), V
CC
IS
2.97
TO
5.5V.........................38
F
IGURE
14. C
LOCK
T
IMING
............................................................................................................................................................. 39
F
IGURE
15. M
ODEM
I
NPUT
/O
UTPUT
T
IMING
F
OR
C
HANNELS
A-D .................................................................................................... 40
F
IGURE
16. 16 M
ODE
(I
NTEL
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D.................................................................................... 40
F
IGURE
17. 16 M
ODE
(I
NTEL
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D.................................................................................. 41
F
IGURE
18. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
R
EAD
T
IMING
FOR
C
HANNELS
A-D........................................................................... 41
F
IGURE
19. 68 M
ODE
(M
OTOROLA
) D
ATA
B
US
W
RITE
T
IMING
FOR
C
HANNELS
A-D ......................................................................... 42
F
IGURE
20. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D ............................................................ 42
F
IGURE
21. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[N
ON
-FIFO M
ODE
]
FOR
C
HANNELS
A-D .......................................................... 43
F
IGURE
22. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA D
ISABLED
]
FOR
C
HANNELS
A-D........................................... 43
F
IGURE
23. R
ECEIVE
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA E
NABLED
]
FOR
C
HANNELS
A-D............................................ 44
F
IGURE
24. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
D
ISABLED
]
FOR
C
HANNELS
A-D............................... 45
F
IGURE
25. T
RANSMIT
R
EADY
& I
NTERRUPT
T
IMING
[FIFO M
ODE
, DMA M
ODE
E
NABLED
]
FOR
C
HANNELS
A-D ............................... 45
P
ACKAGE
D
IMENSIONS
.................................................................................................................................46
R
EVISION
H
ISTORY
.......................................................................................................................................49
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
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