參數(shù)資料
型號： ST16C654IQ64
廠商： EXAR CORP
元件分類： 微控制器/微處理器
英文描述： 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
中文描述： 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64
文件頁數(shù)： 50/51頁
文件大?。?/td> 968K
代理商： ST16C654IQ64
ST16C654/654D
REV. 5.0.0
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
I
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
F
EATURES
.....................................................................................................................................................1
A
PPLICATIONS
...............................................................................................................................................1
F
IGURE
1. ST16C654 B
LOCK
D
IAGRAM
........................................................................................................................................... 1
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
100-
PIN
QFP P
ACKAGES
I
N
16
AND
68 M
ODE
....................................................................... 2
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
PLCC P
ACKAGES
I
N
16
AND
68 M
ODE
AND
TQFP P
ACKAGES
............................................... 3
ORDERING
INFORMATION
................................................................................................................................3
PIN DESCRIPTIONS .........................................................................................................4
1.0 PRODUCT DESCRIPTION ....................................................................................................................8
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................9
2.1 CPU INTERFACE ............................................................................................................................................. 9
F
IGURE
4. ST16C654/654D T
YPICAL
I
NTEL
/M
OTOROLA
D
ATA
B
US
I
NTERCONNECTIONS
................................................................... 9
2.2 DEVICE RESET .............................................................................................................................................. 10
2.3 CHANNEL SELECTION ................................................................................................................................. 10
T
ABLE
1: C
HANNEL
A-D S
ELECT
IN
16 M
ODE
................................................................................................................................. 10
T
ABLE
2: C
HANNEL
A-D S
ELECT
IN
68 M
ODE
................................................................................................................................. 10
2.4 CHANNELS A-D INTERNAL REGISTERS .................................................................................................... 11
2.5 INT OUPUTS FOR CHANNELS A-D .............................................................................................................. 11
2.6 DMA MODE .................................................................................................................................................... 11
T
ABLE
3: INT P
INS
O
PERATION
FOR
T
RANSMITTER
FOR
C
HANNELS
A-D ......................................................................................... 11
T
ABLE
4: INT P
IN
O
PERATION
FOR
R
ECEIVER
FOR
C
HANNELS
A-D................................................................................................. 11
2.7 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 12
F
IGURE
5. T
YPICAL
OSCILLATOR
CONNECTIONS
............................................................................................................................... 12
2.8 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 12
T
ABLE
5: TXRDY#
AND
RXRDY# O
UTPUTS
IN
FIFO
AND
DMA M
ODE
FOR
C
HANNELS
A-D ........................................................... 12
2.9 TRANSMITTER ............................................................................................................................................... 13
2.9.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 13
F
IGURE
6. B
AUD
R
ATE
G
ENERATOR
AND
P
RESCALER
..................................................................................................................... 13
T
ABLE
6: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
...................................................................... 13
2.9.2 TRANSMITTER OPERATION IN NON-FIFO MODE.................................................................................................. 14
2.9.3 TRANSMITTER OPERATION IN FIFO MODE ........................................................................................................... 14
F
IGURE
7. T
RANSMITTER
O
PERATION
IN
NON
-FIFO M
ODE
.............................................................................................................. 14
F
IGURE
8. T
RANSMITTER
O
PERATION
IN
FIFO
AND
F
LOW
C
ONTROL
M
ODE
..................................................................................... 14
2.10 RECEIVER .................................................................................................................................................... 15
2.10.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 15
F
IGURE
9. R
ECEIVER
O
PERATION
IN
NON
-FIFO M
ODE
.................................................................................................................... 15
2.11 AUTO RTS HARDWARE FLOW CONTROL ............................................................................................... 16
2.12 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
F
IGURE
10. R
ECEIVER
O
PERATION
IN
FIFO
AND
A
UTO
RTS F
LOW
C
ONTROL
M
ODE
....................................................................... 16
F
IGURE
11. A
UTO
RTS
AND
CTS F
LOW
C
ONTROL
O
PERATION
....................................................................................................... 17
T
ABLE
7: A
UTO
RTS/CTS F
LOW
C
ONTROL
.................................................................................................................................... 17
2.13 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18
2.14 SPECIAL CHARACTER DETECT ............................................................................................................... 18
T
ABLE
8: A
UTO
X
ON
/X
OFF
(S
OFTWARE
) F
LOW
C
ONTROL
............................................................................................................... 18
2.15 INFRARED MODE ........................................................................................................................................ 19
F
IGURE
12. I
NFRARED
T
RANSMIT
D
ATA
E
NCODING
AND
R
ECEIVE
D
ATA
D
ECODING
.......................................................................... 19
2.16 SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 20
2.17 INTERNAL LOOPBACK .............................................................................................................................. 20
F
IGURE
13. I
NTERNAL
L
OOP
B
ACK
IN
C
HANNEL
A
AND
B ................................................................................................................ 21
3.0 UART INTERNAL REGISTERS ...........................................................................................................22
T
ABLE
9: UART CHANNEL A AND B UART INTERNAL REGISTERS..................................................................................... 22
T
ABLE
10: INTERNAL REGISTERS DESCRIPTION. S
HADED
BITS
ARE
ENABLED
WHEN
EFR B
IT
-4=1....................................... 23
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 25
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
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