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參數(shù)資料
| 型號： | ST16C654IQ64 |
| 廠商： | EXAR CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO |
| 中文描述： | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, LQFP-64 |
| 文件頁數(shù)： | 26/51頁 |
| 文件大?。?/td> | 968K |
| 代理商： | ST16C654IQ64 |
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ST16C654/654D
2.97V TO 5.5V QUAD UART WITH 64-BYTE FIFO
REV. 5.0.0
26
IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1)
Logic 0 = Disable the CTS# interrupt (default).
Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from
low to high (if enabled by EFR bit-7).
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table,
Table 11
, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1
Interrupt Generation:
LSR is by any of the LSR bits 1, 2, 3 and 4.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty.
MSR is by any of the MSR bits 0, 1, 2 and 3.
Receive Xoff/Special character is by detection of a Xoff or Special character.
CTS# is when the remote transmitter toggles the input pin (from low to high) during auto CTS flow control.
RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control.
4.4.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register (LSR bits 1-4 will clear but LSR bit-7 will not clear until
character(s) that generated the interrupt(s) has been emptied or cleared from FIFO).
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff interrupt is cleared by a read to ISR.
Special character interrupt is cleared by a read to ISR register or after next character is received.
RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
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