參數(shù)資料
型號: ST16C452IJ68
廠商: EXAR CORP
元件分類: 微控制器/微處理器
英文描述: DUAL UART WITH PARALLEL PRINTER PORT
中文描述: 2 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68
封裝: PLASTIC, LCC-68
文件頁數(shù): 10/30頁
文件大小: 162K
代理商: ST16C452IJ68
10
ST16C452/452PS
Rev. 3.20
The generator divides the input 16X clock by any divisor
from 1 to 2
16
-1. The 452/452PS divides the basic
external clock by 16. The basic 16X clock provides table
rates to support standard and custom applications
using the same system design. The rate table is
configured via the DLL and DLM internal register func-
tions. Customized Baud Rates can be achieved by
selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 5 below, shows the selectable baud rate table
available when using a 1.8432 MHz external clock
input.
Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (1.8432
MHz CLOCK):
Output
Baud Rate
Output
16 x Clock
Divisor
(Decimal)
User
DLM
Program
Value
(HEX)
DLL
16 x Clock
Divisor
(HEX)
Program
Value
(HEX)
50
110
150
300
600
1200
2400
4800
7200
9600
19.2k
38.4k
57.6k
115.2k
2304
1047
768
384
192
96
48
24
16
12
6
3
2
1
900
417
300
180
C0
60
30
18
10
0C
06
03
02
01
09
04
03
01
00
00
00
00
00
00
00
00
00
00
00
17
00
80
C0
60
30
18
10
0C
06
03
02
01
Loop-back Mode
The internal loop-back capability allows onboard diag-
nostics. In the loop-back mode the normal modem
interface pins are disconnected and reconfigured for
loop-back internally. MCR register bits 0-3 are used
for controlling loop-back diagnostic testing. In the
loop-back mode INT enable and MCR bit-2 in the MCR
register (bits 2,3) control the modem -RI and -CD
inputs respectively. MCR signals -DTR and -RTS (bits
0-1) are used to control the modem -CTS and -DSR
inputs respectively. The transmitter output (TX) and
the receiver input (RX) are disconnected from their
associated interface pins, and instead are connected
together internally (See Figure 6). The -CTS, -DSR, -
CD, and -RI are disconnected from their normal
modem control inputs pins, and instead are connected
internally to -DTR, -RTS, INT enable and MCR bit-2.
Loop-back test data is entered into the transmit hold-
ing register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-
back connection. The receive UART converts the
serial data back into parallel data that is then made
相關PDF資料
PDF描述
ST16C452IJ68PS DUAL UART WITH PARALLEL PRINTER PORT
ST16C452CJ68 Power Supply IC; Number of Outputs:1; Supply Voltage Max:5.5V; Package/Case:10-MSOP; Leaded Process Compatible:No; Output Current:150mA; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Power Dissipation:481mW
ST16C452CJ68PS Power Supply IC; Number of Outputs:1; Supply Voltage Max:5.5V; Package/Case:10-MSOP; Leaded Process Compatible:No; Output Current:150mA; Output Voltage Max:1.3V; Peak Reflow Compatible (260 C):No; Power Dissipation:481mW
ST16C452PS Dual UART with Parallel Printer Port(雙通用異步接收器/發(fā)送器(帶并行打印機端口))
ST16C452 Dual UART with Parallel Printer Port(雙通用異步接收器/發(fā)送器(帶并行打印機端口))
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