參數(shù)資料
型號(hào): SST89E54RC-33-C-PIE
廠商: Microchip Technology
文件頁數(shù): 48/71頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 17KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝: 9
系列: FlashFlex®
核心處理器: 8051
芯體尺寸: 8-位
速度: 33MHz
連通性: EBI/EMI,UART/USART
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 16KB(16K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
2011 Silicon Storage Technology, Inc.
DS25088A
10/11
52
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
Table 19:Power Saving Modes
Mode
Initiated by
State of MCU
Exited by
Idle
Software
(Set IDL bit in
PCON)
MOV PCON,
#01H;
CLK is running.
Interrupts, serial port and
timers/counters are active.
Program Counter is stopped.
ALE and PSEN# signals at a
HIGH level during Idle.
All registers remain
unchanged.
Enabled interrupt or hardware reset.
Start of interrupt clears IDL bit and exits
idle mode, after the ISR RETI instruction,
program resumes execution beginning at
the instruction following the one that
invoked idle mode. A user could consider
placing two or three NOP instructions after
the instruction that invokes idle mode to
eliminate any problems. A hardware reset
restarts the device similar to a power-on
reset.
Power-
down
Software
(Set PD bit in
PCON)
MOV PCON,
#02H;
CLK is stopped.
On-chip SRAM and SFR
data is maintained.
ALE and PSEN# signals at a
LOW level during power -
down.
External Interrupts are only
active for
level sensitive interrupts, if
enabled.
Enabled external level sensitive inter-
rupt or hardware reset. Start of inter-
rupt clears PD bit and exits power-
down mode, after the ISR RETI instruc-
tion program resumes execution begin-
ning at the instruction following the one
that invoked power-down mode. A user
could consider placing two or three
NOP instructions after the instruction
that invokes power-down mode to elimi-
nate any problems. A hardware reset
restarts the device similar to a power-
on reset.
T0-0.0 25008
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