- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1969 > SST89E54RC-33-C-PIE (Microchip Technology)IC MCU 8BIT 17KB FLASH 40PDIP PDF資料下載
參數(shù)資料
| 型號(hào)： | SST89E54RC-33-C-PIE |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 37/71頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT 17KB FLASH 40PDIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 系列： | FlashFlex® |
| 核心處理器： | 8051 |
| 芯體尺寸： | 8-位 |
| 速度： | 33MHz |
| 連通性： | EBI/EMI，UART/USART |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲(chǔ)器容量： | 16KB（16K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 包裝： | 管件 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)當(dāng)前第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)
2011 Silicon Storage Technology, Inc.
DS25088A
10/11
42
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
Watchdog timer
The programmable Watchdog Timer (WDT) is for fail safe protection against software deadlock and for
automatic recovery.
The Watchdog timer can be utilized as a watchdog or a timer. To use the Watchdog timer as a watch-
dog, WDRE (WDTC[3]) should be set to “1.” To use the Watchdog timer as a timer only, WDRE should
be set to “0” so that an interrupt will be generated upon timer overflow, and the EWD (IEA[6]) should be
set to “1” in order to enable the interrupt.
Watchdog Timer Mode
To protect the system against software deadlock, WDT (WDTC[1]) should be refreshed within a user-
defined time period. Without a periodic refresh, an internal hardware reset will be initiated when
WDRE (WDTC[3]) = 1). The WDRE bit can only be cleared by a power-on reset.
Any Write to WDTC must be preceded by a correct feed sequence. If WDTON (WDTC[6])=0, SWDT
(WDTC[0]) controls the start or stop of the watchdog. If WDTON = 1, the watchdog starts regardless of
SWDT and cannot be stopped.
The upper 8 bits of the time base register (WDTD) is used as the reload register of the counter. When
WDT (WDTC[1]) is set to “1,” the content of WDTD is loaded into the watchdog counter and the pres-
caler is also cleared.
If a watchdog reset occurs, the internal reset is active for at least one watchdog clock cycle. The code
execution will begin immediately after the reset cycle.
The WDTS flag bit is set by Watchdog timer overflow and can only be cleared by power-on reset.
Users can also clear the WDTS bit by writing “1” to it following a correct feed sequence.
Pure Timer Mode
In Timer mode, the WDTC and WDTD can be written at any time without a feed sequence. Setting or
clearing the SWDT bit will start or stop the counter. A timer overflow will set the WDTS bit. Writing “1”
to this bit clears the bit. When an overflow occurs, the content of WDTD is reloaded into the counter
and the Watchdog timer immediately begins to count again. If the interrupt is enabled, an interrupt will
occur when the timer overflows. The vector address is 053H and it has a second level priority by
default. A feed sequence is not required in this mode.
Clock Source
The WDT in the device uses the system clock (XTAL1) as its time base. So strictly speaking, it is a
watchdog counter rather than a Watchdog timer. The WDT register will increment every 344,064 crys-
tal clocks. The upper 8-bits of the time base register (WDTD) are used as the reload register of the
WDT.
Figure 10 provides a block diagram of the WDT. Two SFRs (WDTC and WDTD) control Watchdog
timer operation.
The time-out period of the WDT is calculated as follows:
Period = (255 - WDTD) * 344064 * 1/fCLK (XTAL1)
where WDTD is the value loaded into the WDTD register and fOSC is the oscillator frequency.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SST89E58RD2-40-I-TQJE | IC MCU 8BIT FLASH 44TQFP |
| SST89V58RD2-33-I-TQJE | IC MCU 8BIT 40KB FLASH 44TQFP |
| SSTUB32S869BHLFT | IC REGIST BUFF 14BIT DDR2 150BGA |
| ST16C1450CJ28-F | IC UART FIFO 1B 28PLCC |
| ST16C2450CJ44-F | IC DUART 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SST89E54RD | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex MCU |
| SST89E54RD2 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E54RD2/RD | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E54RD2-33-C-NI | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
| SST89E54RD2-33-C-NIE1 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:FlashFlex51 MCU |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。