參數(shù)資料
型號(hào)： SST89E54RC-33-C-PIE
廠商： Microchip Technology
文件頁數(shù)： 47/71頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 17KB FLASH 40PDIP
標(biāo)準(zhǔn)包裝： 9
系列： FlashFlex®
核心處理器： 8051
芯體尺寸： 8-位
速度： 33MHz
連通性： EBI/EMI，UART/USART
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 16KB（16K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 512 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
振蕩器型： 外部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
2011 Silicon Storage Technology, Inc.
DS25088A
10/11
51
FlashFlex MCU
SST89E52RC / SST89E54RC
Data Sheet
A Microchip Technology Company
Power-Saving Modes
The device provides two power saving modes of operation for applications where power consumption
is critical. The two modes are idle and power-down, see Table 19.
In addition to these two power saving modes, users can choose to set the device to run at one of four
slower clock rates to reduce power consumption. See Section , “Clock Divider Option”.
Another option is to turn off the clocks by individual functional blocks, please refer to Section , the PMC
register definition, for detailed information.
Idle Mode
Idle mode is entered setting the IDL bit in the PCON register. In idle mode, the program counter (PC) is
stopped. The system clock continues to run and all interrupts and peripherals remain active. The on-
chip RAM and the special function registers hold their data during this mode.
The device exits idle mode through either a system interrupt or a hardware reset. Exiting idle mode via
system interrupt, the start of the interrupt clears the IDL bit and exits idle mode. After exit the Interrupt
Service Routine, the interrupted program resumes execution beginning at the instruction immediately
following the instruction which invoked the idle mode. A hardware reset starts the device similar to a
power-on reset.
Power-down Mode
The power-down mode is entered by setting the PD bit in the PCON register. In the power-down mode, the clock
is stopped and external interrupts are active for level sensitive interrupts only. SRAM contents are retained during
power-down, the minimum VDD level is 2.0V.
The device exits power-down mode through either an enabled external level sensitive interrupt or a
hardware reset. The start of the interrupt clears the PD bit and exits power-down. Holding the external
interrupt pin low restarts the oscillator, the signal must hold low at least 1024 clock cycles before bring-
ing back high to complete the exit. Upon interrupt signal restored to logic VIH, the interrupt service rou-
tine program execution resumes beginning at the instruction immediately following the instruction
which invoked power-down mode. A hardware reset starts the device similar to power-on reset.
To exit properly out of power-down, the reset or external interrupt should not be executed before the VDD
line is restored to its normal operating voltage. Be sure to hold VDD voltage long enough at its normal oper-
ating level for the oscillator to restart and stabilize (normally less than 10 ms).
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