參數(shù)資料
型號： SST55VD020-60-I-TQWE
廠商： SILICON STORAGE TECHNOLOGY INC
元件分類： 存儲控制器/管理單元
英文描述： IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100
封裝： 14 X 14 MM, ROHS COMPLIANT, MS-026, TQFP-100
文件頁數(shù)： 44/45頁
文件大?。?/td> 666K
代理商： SST55VD020-60-I-TQWE
8
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
IORD#
19
E9
I
I2Z
IORD#: This is an I/O Read Strobe generated by the host. When
Ultra DMA mode is not active, this signal gates I/O data from the
device.
HDMARDY#
HDMARDY#: In Ultra DMA mode when DMA Read is active, this
signal is asserted by the host to indicate that the host is ready to
receive Ultra DMA data-in bursts. The host may negate
HDMARDY# to pause an Ultra DMA transfer.
HSTROBE
HSTROBE: When DMA Write is active, this signal is the data-out
strobe generated by the host. Both the rising and falling edges of
HSTROBE cause data to be latched by the device. The host may
stop generating HSTROBE edges to pause an Ultra DMA data-out
burst.
IOWR#
57
D1
I
I2Z
This is an I/O Write Strobe generated by the host. When Ultra
DMA mode is not active, this signal is used to clock I/O data into
the device.
STOP
When Ultra DMA mode protocol is active, the assertion of this sig-
nal causes the termination of the Ultra DMA burst
IOCS16#
55
C2
O
O2
This output signal is asserted low when the device is indicating a
word data transfer cycle.
INTRQ
21
D10
O
O1
This signal is the active high Interrupt Request to the host.
PDIAG#
54
C1
I/O
I1U/O1
The Pass Diagnostic signal in the Master/Slave handshake proto-
col.
DASP#
75
H2
I/O
I1U/O6
The Drive Active/Slave Present signal in the Master/Slave hand-
shake protocol.
RESET#
1
K10
I
I2U
This input pin is the active low hardware reset from the host.
WP#/PD#
97
H7
I
I3U
The WP#/PD# pin can be used for either the Write Protect mode or
Power-down mode, but only one mode is active at any time. The
Write Protect or Power-down modes can be selected through the
host command. The Write Protect mode is the factory default set-
ting.
This pin accepts only in the 3.3V VDD signal level.
Flash Media Interface
FRE#
84
H3
OO5
Active Low Flash Media Chip Read
FWE#
96
J7
Active Low Flash Media Chip Write
FCLE
92
K6
Active High Flash Media Chip Command Latch Enable
FALE
94
H6
Active High Flash Media Chip Address Latch Enable
FAD15
46
A3
I/O
I3U/O5
Flash Media Chip High Byte Address/Data Bus pins
FAD14
44
B4
FAD13
42
C5
FAD12
40
A5
FAD11
35
C7
FAD10
33
A7
FAD9
31
B8
FAD8
29
B9
TABLE
1: Pin Assignments (Continued) (2 of 4)
Symbol
Pin No.
Pin
Type
I/O
Type1
Name and Functions
100-
TQFP
85-
VFBGA
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