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| 型號： | SST55VD020-60-I-TQWE |
| 廠商： | SILICON STORAGE TECHNOLOGY INC |
| 元件分類： | 存儲控制器/管理單元 |
| 英文描述： | IDE COMPATIBLE, FLASH MEMORY DRIVE CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, ROHS COMPLIANT, MS-026, TQFP-100 |
| 文件頁數(shù)： | 10/45頁 |
| 文件大?。?/td> | 666K |
| 代理商： | SST55VD020-60-I-TQWE |
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18
Data Sheet
NAND Controller
SST55VD020
2009 Silicon Storage Technology, Inc.
S71355-03-000
07/09
Status & Alternate Status Registers (Read Only)
These registers return the NAND Controller status when read by the host. Reading the Status register does clear a
pending interrupt while reading the alternate Status register does not. The meaning of the status bits are described as
follows:
Symbol
Function
BUSY
The busy bit is set when the NAND Controller has access to the command buffer and
registers and the host is locked out from accessing the Command register and buffer. No
other bits in this register are valid when this bit is set to a 1.
RDY
RDY indicates whether the device is capable of performing NAND Controller operations.
This bit is cleared at power up and remains cleared until the NAND Controller is ready to
accept a command.
DWF
This bit, if set, indicates a write fault has occurred.
DSC
This bit is set when the NAND Controller is ready.
DRQ
The Data-Request bit is set when the NAND Controller requires that information be
transferred either to or from the host through the Data register.
CORR
This bit is set when a correctable data error has been encountered and the data has
been corrected. This condition does not terminate a multi-sector Read operation.
ERR
This bit is set when the previous command has ended in some type of error. The bits in
the Error register contain additional information describing the error. It is required that
the host retry any media access command (such as Read-Sectors and Write-Sectors)
that end with an error condition.
Device Control Register (Write Only)
This register is used to control the NAND Controller interrupt request and to issue a software reset. This register
can be written to even if the device is busy. The bits are defined as follows:
Symbol
Function
SW Rst
This bit is set to 1 in order to force the NAND Controller to perform a software Reset
operation. The chip remains in reset until this bit is reset to ‘0.’
-IEn
0: The Interrupt Enable bit enables interrupts
1: Interrupts from the NAND Controller are disabled
This bit is set to 0 at Power-on and Reset.
Command Register (Write Only)
This register contains the command code being sent to the drive. Command execution begins immediately after
this register is written. The executable commands, the command codes, and the necessary parameters for each
command are listed in Table 7.
NAND Controller Command Description
This section defines the software requirements and the format of the commands the host sends to the NAND Controller.
Commands are issued to the NAND Controller by loading the required registers in the command block with the supplied
parameters, and then writing the command code to the Command register. With the exception of commands listed in
Sections -, NAND Controller complies with ATA-6 Specifications.
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
BUSY
RDY
DWF
DSC
DRQ
CORR
0
ERR
1000 0000b
D7
D6
D5
D4
D3
D2
D1
D0
Reset Value
XXX
X
1
SW Rst
-IEn
0
0000 1000b
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| SST55VD020-60-I-TQWE-TM024 | 功能描述:閃存 ATA Media 60MHz 3.3V Industrial RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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| SST58LD008-70-C-P1H | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
| SST58LD016 | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
| SST58LD016-70-C-P1H | 制造商:SST 制造商全稱:Silicon Storage Technology, Inc 功能描述:ATA-Disk Chip |
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