參數(shù)資料
型號： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 8/153頁
文件大小： 863K
代理商： SSD1905QT2
viii
List of Tables
Table 3-1 : Ordering Information...................................................................................................................3
Table 4-1 : TQFP Pin Assignment Table......................................................................................................6
Table 5-1 : Host Interface Pin Descriptions ..................................................................................................7
Table 5-2 :
LCD Interface Pin Descriptions
..............................................................................................9
Table 5-3 : Clock Input Pin Descriptions.....................................................................................................10
Table 5-4 : Miscellaneous Pin Descriptions................................................................................................10
Table 5-5 : Power And Ground Pin Descriptions........................................................................................10
Table 5-6 : Summary of Power-On/Reset Options .....................................................................................11
Table 5-7 : Host Bus Interface Pin Mapping...............................................................................................11
Table 5-8 : LCD Interface Pin Mapping.......................................................................................................12
Table 5-9 : Data Bus Organization..............................................................................................................13
Table 5-10 : Pin State Summary.................................................................................................................13
Table 7-1 : MCLK Divide Selection.............................................................................................................16
Table 7-2 : PCLK Divide Selection..............................................................................................................17
Table 7-3 : PCLK Source Selection ............................................................................................................17
Table 7-4 : Panel Data Width Selection......................................................................................................21
Table 7-5 : Active Panel Resolution Selection............................................................................................22
Table 7-6 : LCD Panel Type Selection........................................................................................................22
Table 7-7 :
Color Invert Mode Options
....................................................................................................32
Table 7-8 :
LCD Bit-per-pixel Selection
..................................................................................................33
Table 7-9 : Display Rotate Mode Select Options........................................................................................34
Table 7-10 : 32-bit Address X Increments for Various Color Depths..........................................................38
Table 7-11 : 32-bit Address Y Increments for Various Color Depths..........................................................39
Table 7-12 : 32-bit Address X Increments for Various Color Depths..........................................................40
Table 7-13 : 32-bit Address Y Increments for Various Color Depths..........................................................41
Table 7-14 : PWM Clock Control.................................................................................................................46
Table 7-15 : CV Pulse Control ....................................................................................................................47
Table 7-16 : PWM Clock Divide Select Options..........................................................................................47
Table 7-17 : CV Pulse Divide Select Options .............................................................................................48
Table 7-18 : PWM Duty Cycle Select Options............................................................................................49
Table 7-19 : X Increment Mode for Various Color Depths..........................................................................52
Table 7-20 : Y Increment Mode for Various Color Depths..........................................................................53
Table 8-1 : Absolute Maximum Ratings......................................................................................................60
Table 8-2 : Recommended Operating Conditions ......................................................................................60
Table 9-1 : Electrical Characteristics for IOV
DD
= 3.3V typical....................................................................61
Table 10-1 : Clock Input Requirements for CLKI........................................................................................62
Table 10-2 : Clock Input Requirements for AUXCLK..................................................................................63
Table 10-3 : Internal Clock Requirements ..................................................................................................63
Table 10-4 : Generic #1 Interface Timing ...................................................................................................65
Table 10-5 : Generic #2 Interface Timing ...................................................................................................67
Table 10-6 : Motorola MC68K #1 Interface Timing.....................................................................................69
Table 10-7 : Motorola DragonBall Interface with DTACK# Timing .............................................................71
Table 10-8 : Motorola DragonBall Interface without DTACK# Timing ........................................................73
Table 10-9 : Hitachi SH-3 Interface Timing.................................................................................................75
Table 10-10 : Hitachi SH-4 Interface Timing...............................................................................................77
Table 10-11 : Passive/TFT Power-On Sequence Timing ...........................................................................78
Table 10-12 : Passive/TFT Power-Off Sequence Timing ...........................................................................79
Table 10-13 : Power Saving Status Timing.................................................................................................80
Table 10-14 : Panel Timing Parameter Definition and Register Summary.................................................81
Table 10-15 : Monochrome 4-Bit Panel A.C. Timing ..................................................................................86
Table 10-16 : Monochrome 8-Bit Panel A.C. Timing ..................................................................................89
Table 10-17 : Color 4-Bit Panel A.C. Timing...............................................................................................92
Table 10-18 : Color 8-Bit Panel A.C. Timing (Format stripe)......................................................................95
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