參數(shù)資料
型號: SSD1905QT2
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Graphics Controller CMOS
中文描述: LCD圖形控制器的CMOS
文件頁數(shù): 76/153頁
文件大?。?/td> 863K
代理商: SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
67
Table 10-5 : Generic #2 Interface Timing
Symbol
f
BUSCLK
T
BUSCLK
t
1
t
2
t
3
Parameter
Min
Max
66
Units
MHz
ns
ns
ns
ns
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge
where CS# = 0 and either MEMR# = 0 or MEMW# = 0
SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW#
rising edge
CS# setup to BUSCLK rising edge
CS# hold from either MEMR# or MEMW# rising edge
MEMR# or MEMW# asserted for MCLK = BCLK
MEMR# or MEMW# asserted for MCLK = BCLK
÷
2
MEMR# or MEMW# asserted for MCLK = BCLK
÷
3
1/f
BUSCLK
6
6
1
t
4
0
ns
t
5
t
6
t
7a
t
7b
t
7c
1
0
ns
ns
13
18
23
T
BUSCLK
T
BUSCLK
T
BUSCLK
T
BUSCLK
ns
ns
t
7d
MEMR# or MEMW# asserted for MCLK = BCLK
÷
4
28
t
8
t
9
MEMR# or MEMW# setup to BUSCLK rising edge
Falling edge of either MEMR# or MEMW# to IOCHRDY driven
low
Rising edge of either MEMR# or MEMW# to IOCHRDY high
impedance
SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and
MEMW#=0 (write cycle)(see note1)
SD[15:0] hold from IOCHRDY rising edge (write cycle)
MEMR# falling edge to SD[15:0] driven (read cycle)
IOCHRDY rising edge to SD[15:0] valid (read cycle)
Rising edge of MEMR# to SD[15:0] high impedance (read
cycle)
1
3
15
t
10
3
13
ns
t
11
0
ns
t
12
t
13
t
14
t
15
0
3
3
ns
ns
ns
ns
13
2
12
1. t
11
is the delay from when data is placed on the bus until the data is latched into the write buffer.
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