參數(shù)資料
型號： SSD1905QT2
廠商： Electronic Theatre Controls, Inc.
英文描述： LCD Graphics Controller CMOS
中文描述： LCD圖形控制器的CMOS
文件頁數(shù)： 16/153頁
文件大?。?/td> 863K
代理商： SSD1905QT2
SSD1905
Rev 1.3
10/2002
SOLOMON
7
5.1
Host Interface
Table 5-1 : Host Interface Pin Descriptions
Pin Name Type
TQFP
Pin #
Cell
RESET#
State
Description
A0
I
5
LIS
0
This input pin has multiple functions.
For Generic #1, this pin is not used and should be
connected to V
SS
.
For Generic #2, this is an input of system address bit 0
(A0).
For MC68K #1, this is an input of the lower data strobe
(LDS#).
For DragonBall, this pin is not used and should be
connected to V
SS
.
For SH-3/SH-4, this pin is not used and should be
connected to VSS.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
A[16:1]
I
2-4, 87-
99
LIS
0
System address bus bits 16-1.
D[15:0]
IO
18-24,
27-35
LB2
Hi-Z
Input data from the system data bus.
For Generic #1, these pins are connected to D[15:0].
For Generic #2, these pins are connected to D[15:0].
For MC68K #1, these pins are connected to D[15:0].
For DragonBall, these pins are connected to D[15:0].
For SH-3/SH-4, these pins are connected to D[15:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
For Generic #1, this is an input of the write enable signal
for the lower data byte (WE0#).
For Generic #2, this is an input of the write enable signal
(WE#).
For MC68K #1, this pin must be tied to IOV
DD
.
For DragonBall, this is an input of the byte enable signal
for the D[7:0] data byte (LWE#).
For SH-3/SH-4, this is input of the write enable signal for
data D[7:0].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
This input pin has multiple functions.
For Generic #1, this is an input of the write enable signal
for the upper data byte (WE1#).
For Generic #2, this is an input of the byte enable signal
for the high data byte (BHE#).
For MC68K #1, this is an input of the upper data strobe
(UDS#).
For DragonBall, this is an input of the byte enable signal
for the D[15:8] data byte (UWE#).
For SH-3/SH-4, this is input of the write enable signal for
data D[15:8].
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
Chip select input. See Table 5-7 : Host Bus Interface Pin
Mapping for summary.
This input pin is used to select the display buffer or internal
registers of the SSD1905. M/R# is set high to access the
display buffer and low to access the registers.
See Table 5-7 : Host Bus Interface Pin Mapping for summary.
WE0#
I
10
LIS
1
WE1#
I
11
LIS
1
CS#
I
6
LIS
1
M/R#
I
7
LIS
0
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