參數(shù)資料
型號： SPL505YC264BT
元件分類： 時鐘產(chǎn)生/分配
英文描述： 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝： 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件頁數(shù)： 21/27頁
文件大小： 314K
代理商： SPL505YC264BT
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 3 of 27
31
SRC9#
O, DIF 100 MHz Differential serial reference clocks.
32
SRC11#/OE#_9
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#9 Input controlling SRC9
Default SRC11.
33
SRC11/OE#_10
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#10 Input controlling
SRC10. Default SRC11.
34
SRC10
O, DIF 100 MHz Differential serial reference clocks.
35
SRC#10
O, DIF 100 MHz Differential serial reference clocks.
36
VDD_SRC_IO
PWR
0.7V Power supply for SRC outputs.
37
SRC5#CPU_STOP#
I/O,
Dif
3.3V tolerant input for stopping CPU outputs/100 MHz Differential serial
reference clocks.
38
SRC5/PCI_STOP#
I/O,
Dif
3.3V tolerant input for stopping PCI and SRC outputs/100 MHz Differential
serial reference clocks.
39
VDD_SRC
PWR
3.3V Power supply for SRC PLL.
40
SRC6#
O, DIF 100 MHz Differential serial reference clocks.
41
SRC6
O, DIF 100 MHz Differential serial reference clocks.
42
VSS_SRC
GND
Ground for outputs.
43
SRC7#/OE#_6
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#6 Input controlling
SRC6. Default SRC7.
44
SRC7/OE#_8
I/O,
Dif
100 MHz Differential serial reference clocks/3.3V OE#8 Input controlling
SRC8. Default SRC7.
45
VDD_SRC_IO
PWR
0.7V power supply for SRC outputs.
46
SRC8#/CPUC2_ITP#
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
47
SRC8/CPUT2_ITP
O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ CK_PWRGD
assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
Note: CPU2 is an iAMT clock in iAMT mode depending on the configuration set in Byte
11 Bit3:2.
48
IO_VOUT
O
Integrated Linear Regulator Control.
49
VDD_CPU_IO
PWR
0.7V Power supply for CPU outputs.
50
CPU1#
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
51
CPU1
O, DIF Differential CPU clock outputs. Note: CPU1 is an iAMT clock in iAMT mode
depending on the configuration set in Byte 11 Bit3:2.
52
VSS_CPU
GND
Ground for outputs.
53
CPU#0
O, DIF Differential CPU clock outputs.
54
CPU0
O, DIF Differential CPU clock outputs.
55
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
56
CK_PWRGD/PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, FS_D, SRC5_SEL, and ITP_EN.
After CK_PWRGD (active HIGH) assertion, this pin becomes a real-time input
for asserting power down (active LOW).
57
FSB/TEST_MODE
I
3.3V tolerant input for CPU frequency selection.
Selects Ref/N or Tri-state when in test mode
0 = Tri-state, 1 = Ref/N.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifica-
tions.
58
VSS_REF
GND
Ground for outputs.
Pin Definitions (continued)
Pin No.
Name
Type
Description
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