參數(shù)資料
型號: SPL505YC264BT
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6 X 17 MM, LEAD FREE, MO-153, TSSOP-64
文件頁數(shù): 1/27頁
文件大?。?/td> 314K
代理商: SPL505YC264BT
Clock Generator for Intel
Bearlake Chipset
SPL505YC264BT
Rev 1.4 May 21, 2007
Page 1 of 27
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
www.SpectraLinear.com
Features
Compliant to Intel CK505
Selectable CPU frequencies
Differential CPU clock pairs
100 MHz Differential SRC clocks
100 MHz Differential LCD clock
96 MHz Differential Dot clock
48 MHz USB clocks
33 MHz PCI clock
25 MHz WOL or PATA clock
27 MHz non-spread Video Clock
Buffered Reference Clock 14.318 MHz
Low-voltage frequency select input
I2C support with readback capabilities
Triangular Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
3.3V Power supply/0.7V for Diff IOs
64-pin TSSOP package
Table 1. Output Configuration Table
CPU
SRC
PCI REF DOT96 USB_48M
LCD
x2/x3
x8/12
x6
x 1
x1
Pin Configuration
Block Diagram
PCI_0 / OE#_0/2_A
1
64
SCLK
VDD_PCI
2
63
SDATA
PCI_1 / OE#_1/4_A
3
62
REF0/FSC/TEST_SEL
PCI_2 / TME
4
61
VDD_REF
PCI_3 / CFG0*
5
60
XTAL_IN
PCI_4 / SRC5_EN
6
59
XTAL_OUT
PCIF_0 / ITP_EN
7
58
VSS_REF
VSS_PCI
8
57
FSB / TEST_MODE
VDD_48
9
56
CK_PWRGD / PWRDWN#
USB_48 / FSA
10
55
VDD_CPU
VSS_48
11
54
CPU0
VDD_IO
12
53
CPU0#
SRC0 / DOT96
13
52
VSS_CPU
SRC0# / DOT96#
14
51
CPU1
VSS_IO
15
50
CPU1#
VDD_PLL3
16
49
VDD_CPU_IO
SRC1 / LCD_100 / SE1
17
48
IO_VOUT
SRC1#/ LCDC_100#/SE2
18
47
SRC8 / CPU2_ITP
VSS_PLL3
19
46
SRC8# / CPU2_ITP#
VDD_PLL3_IO
20
45
VDD_SRC_IO
SRC2 / SATA
21
44
SRC7 / OE#_8
SRC2# / SATA#
22
43
SRC7# / OE#_6
VSS_SRC
23
42
VSS_SRC
SRC3 / OE#_0/2_B
24
41
SRC6
SRC3# / OE#_1/4_B
25
40
SRC6#
VDD_SRC_IO
26
39
VDD_SRC
SRC4
27
38
SRC5 / PCI_STOP#
SRC4#
28
37
SRC5# / CPU_STOP#
VSS_SRC
29
36
VDD_SRC_IO
SRCT9
30
35
SRC10#
SRCC9
31
34
SRC10
SRC11# / OE#_9
32
33
SRC11 / OE#_10
* Internal Pull-Down
S
P
L
5
0
5
Y
C
2
6
4
B
T
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