參數(shù)資料
型號: SP9842KS
英文描述: 8-Bit Octal, 2-Quadrant Multiplying, BiCMOS DAC
中文描述: 8位八路,2象限乘法,BiCMOS工藝援
文件頁數(shù): 18/32頁
文件大?。?/td> 745K
代理商: SP9842KS
284
When V
is tied to ground, this expression
reduces to:
V
OUT
= (Data/128) *V
IN
Multiplication of Input Voltages
While both the
SP9841
and
SP9842
are capable of
two–quadrant multiplication, this terminology is not
very precise when describing a system which runs
from a single positive supply. Traditionally, the quad-
rants have been defined with respect to 0V. A two–
quadrant multiplying DAC could produce negative
output voltages only if a negative voltage reference
were applied. A four–quadrant device could also
produce a code–controlled negative output from a
positive reference, or a code–controlled positive out-
put from a negative reference. If ground is used to
delineate the quadrants, then the
SP9841/SP9842
should be considered single–quadrant multiplying
devices, as their output op amps cannot produce
voltages below ground.
In reality, it is possible to define a dc voltage as a signal
ground in a single supply system. If the DAC's V
pin is driven to the voltage chosen as pseudoground,
then each voltage output will exhibit 2–quadrant
behavior with respect to pseudoground; that is the
output voltage will enter the quadrant below the
pseudoground only when the reference input voltage
goes below pseudoground. This mode of operation is
useful when implementing programmable gain/at-
tenuator sections, especially when the input signal is
bipolar with respect to pseudoground, or is ac–
coupled into the V
(X) pin. When V
is tied to
power supply ground, only output voltages greater
than V
are possible, and the device performs
single–quadrant multiplication, much like a buffered
programmable trimpot across a single supply.
Fig-
ures 2a
and
2b
show single–quadrant and 2–quadrant
performance of the
SP9841/SP9842
. Applications
which require 4–quadrant operation with respect to
pseudoground should use the
SIPEX SP9840
or
SP9843
4–quadrant multiplying DACs.
The choice of voltage to use for the pseudoground is
limited by the legal voltage swing at the op amp
output. The op amp exhibits excellent linearity for
output voltages between, conservatively, 100mV and
V
– 1.5V. The op amp BiCMOS output stage
consists of an npn follower loaded by an NMOS
common sourced to ground. This circuit exhibits
wide bandwidth and can source large currents, while
retaining the capability of driving the output to volt-
ages close to ground.
At output voltages below 25mV, feedback forces
some op amp internal nodes toward the supply rails.
The NMOS pull–down device gets driven hard and
the NMOS device enters the linear range — it begins
to function in the same manner as a 50 ohm resistor.
In reality, the wideband amplifier output stage sinks
some internal quiescent current even when driving the
output towards ground. This sunk current drops
across the output stage NMOS transistor ON–resis-
tance and internal routing resistance to provide a
minimum output voltage, below which the amplifier
cannot drive. This minimum voltage is in the 15
to 25mV range. It varies within a package with
each op amp's offset voltage and biasing varia-
tions. If an input voltage lower than this mini-
mum, such as code 0 or 1, when V
REFL
is ground,
2.5
1.5
0
V
I
V
REFL
(Volts)
0.5
1.0
2.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
DD
= 4.75V minimum; V
OUTMAX
< +3.25V
2.5
1.5
0
V
I
V
REFL
(Volts)
0.5
1.0
2.0
3.0
0
0.5
1.0
1.5
2.0
2.5
3.0
V
DD
= 4.75V minimum; V
OUTMAX
>100mV
a)
b)
Figure 3. Reference Voltages a) Normal Operation; b) Maximum Linearity Near Code 1
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