參數(shù)資料
型號: SN74LVC1G123YEPR
廠商: TEXAS INSTRUMENTS INC
元件分類: 諧振器
英文描述: LVC/LCX/Z SERIES, MONOSTABLE MULTIVIBRATOR, PBGA8
封裝: DSBGA-8
文件頁數(shù): 11/18頁
文件大?。?/td> 365K
代理商: SN74LVC1G123YEPR
www.ti.com
DECSCRIPTION/ORDERING INFORMATION (CONTINUED)
CLR
Cext
Rext/Cext
R
B
A
Q
1
2
3
7
6
5
SN74LVC1G123
SINGLE RETRIGGERABLE MONOSTABLE MULTIVIBRATOR
WITH SCHMITT-TRIGGER INPUTS
SCES586A – JULY 2004 – REVISED JUNE 2005
The output pulse duration is programmed by selecting external resistance and capacitance values. The external
timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected
between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between
Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates
with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. CLR can be used to override A or
B inputs. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
FUNCTION TABLE
INPUTS
OUTPUTS
Q
CLR
A
B
L
X
L
X
H
X
L(1)
X
L
L(1)
H
L
H
H
L
H
(1)
These outputs are based on the
assumption that the indicated
steady-state conditions at the A
and B inputs have been set up
long enough to complete any
pulse started before the setup.
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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