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參數(shù)資料
| 型號： | SN74ALVTH16543 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 16-Bit Registered Transceivers(2.5V/3.3V16位記錄收發(fā)器) |
| 中文描述： | 2.5-V/3.3-V 16位注冊收發(fā)器（2.5V/3.3V16位記錄收發(fā)器） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 248K |
| 代理商： | SN74ALVTH16543 |
SN54ALVTH16543, SN74ALVTH16543
2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES073A – JUNE 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Outputs (–32 mA/64 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The
transceivers designed for 2.5-V or 3.3-V V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment. These
devices can be used as two 8-bit transceivers or
one 16-bit transceiver. Separate latch-enable
(LEAB or LEBA), output-enable (OEAB or OEBA),
and chip-enable (CEAB or CEBA) inputs are
provided for each register to permit independent
control in either direction of data flow.
’ALVTH16543
are
16-bit
registered
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to A is similar but uses the CEBA, LEBA, and OEBA inputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVTH16543 is available in TI’s thin very small-outline package (DGV), which provides the same I/O
pin count and functionality of standard Widebus packages in less than half the printed circuit board area.
The SN54ALVTH16543 is characterized for operation over the full military temperature range of –55
°
C to
125
°
C. The SN74ALVTH16543 is characterized for operation from –40
°
C to 85
°
C.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
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1OEAB
1LEAB
1CEAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CEAB
2LEAB
2OEAB
1OEBA
1LEBA
1CEBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CEBA
2LEBA
2OEBA
SN54ALVTH16543 . . . WD PACKAGE
SN74ALVTH16543 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN54ALVTH16601 | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN54ALVTH16601WD | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN74ALVTH16601DGG | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN74ALVTH16601DGV | 2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS |
| SN54ALVTH16646 | 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs( 2.5V/3.3V 16位總線收發(fā)器(三態(tài)輸出)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SN74ALVTH16601DL | 功能描述:通用總線函數(shù) 2.5/3.3V 18-Bit Univ Bus Trncvr W/3St Otp RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601DLR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601GR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16601VR | 功能描述:通用總線函數(shù) 2.5/3.3V 18bit Univ RoHS:否 制造商:Texas Instruments 邏輯類型:CMOS 邏輯系列:74VMEH 電路數(shù)量:1 開啟電阻（最大值）: 傳播延遲時間:10.1 ns 電源電壓-最大:3.45 V 電源電壓-最小:3.15 V 最大工作溫度:+ 85 C 最小工作溫度:0 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| SN74ALVTH16821DL | 功能描述:觸發(fā)器 2.5/3.3V 20bit Univ RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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