參數(shù)資料
型號(hào)： SN54LVTH182502A
廠商： Texas Instruments, Inc.
英文描述： 3.3-V ABT Scan Test Device With 18-Bit Universal Bus Transceivers(3.3VABT掃描測(cè)試裝置(18位通用總線收發(fā)器))
中文描述： 的3.3V ABT生根粉掃描測(cè)試設(shè)備與18位通用總線收發(fā)器（3.3VABT掃描測(cè)試裝置（18位通用總線收發(fā)器））
文件頁(yè)數(shù)： 11/35頁(yè)
文件大?。?/td> 806K
代理商： SN54LVTH182502A
SN54LVTH18502A, SN54LVTH182502A, SN74LVTH18502A, SN74LVTH182502A
3.3-V ABT SCAN TEST DEVICES
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS668A – JULY 1996 – REVISED DECEMBER 1996
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
boundary-control register
The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test
(RUNT) instruction to implement additional test operations not included in the basic SCOPE
instruction set.
Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that
are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.
Bit 0
(LSB)
TDO
TDI
Bit 1
Bit 2
(MSB)
Figure 3. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
Bit 0
TDO
TDI
Figure 4. Bypass Register Order of Scan
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