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參數(shù)資料
| 型號： | SN54ALVTH16543 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 16-Bit Registered Transceivers( 2.5V/3.3V 16位記錄收發(fā)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 16位注冊收發(fā)器（2.5V/3.3V的16位記錄收發(fā)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 248K |
| 代理商： | SN54ALVTH16543 |
SN54ALVTH16543, SN74ALVTH16543
2.5-V/3.3-V 16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES073A – JUNE 1996 – REVISED JULY 1996
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V
0.2 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
2
×
VCC
Open
GND
500
500
tPLH
tPHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VCC/2
VCC/2
VCC/2
VCC/2
VCC
0 V
VCC/2
VCC/2
VOH
VOL
0 V
VCC/2
VOL + 0.3 V
VCC/2
VOH – 0.3 V
0 V
VCC/2
VCC
0 V
VCC/2
VCC/2
0 V
VCC
0 V
VCC/2
VCC/2
tw
Input
VCC
VCC
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2
×
VCC
GND
TEST
S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
10 MHz, ZO = 50
, tr
2.5 ns, tf
2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
P
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| SN74ALVTH16543 | 2.5-V/3.3-V 16-Bit Registered Transceivers(2.5V/3.3V16位記錄收發(fā)器) |
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