參數(shù)資料
型號： SN54ALVTH16240WD
廠商： Texas Instruments, Inc.
元件分類： 基準(zhǔn)電壓源/電流源
英文描述： Power Factor Controller in Critical-Mode Peak-Current-Mode Boost with OVP; Package: 8 LEAD PDIP; No of Pins: 8; Container: Rail; Qty per Container: 50
中文描述： 2.5-V/3.3-V 16位緩沖器/ 3司機(jī)態(tài)輸出
文件頁數(shù)： 1/10頁
文件大?。?/td> 178K
代理商： SN54ALVTH16240WD
SN54ALVTH16240, SN74ALVTH16240
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES138A – JULY 1998 – REVISED JANUARY 1999
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
State-of-the-Art Advanced BiCMOS
Technology (ABT) Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
High Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
CC
)
Power Off Disables Outputs, Permitting
Live Insertion
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16240 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V V
CC
operation, but with
the capability to provide a TTL interface to a 5-V system environment.
These devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
Copyright
1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
SN54ALVTH16240 . . . WD PACKAGE
SN74ALVTH16240 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus is a trademark of Texas Instruments Incorporated.
相關(guān)PDF資料
PDF描述
SN74ALVTH16240DGG 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN74ALVTH16240DGV 2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SN54ALVTH16244 2.5-V/3.3-V 16-Bit Buffers/Drivers(2.5V/3.3V 16位緩沖器/驅(qū)動器(三態(tài)輸出))
SN54ALVTH16245 2.5-V/3.3-V 16-Bit Bus Transceivers With 3-State Outputs(2.5V/3.3V 16位總線收發(fā)器(三態(tài)輸出))
SN54ALVTH162827 2.5-V/3.3-V 20-Bit Buffers/Drivers(2.5V/3.3V 20位緩沖器/驅(qū)動器(三態(tài)輸出))
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