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參數(shù)資料
| 型號(hào)： | SN54ALVTH162827 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 20-Bit Buffers/Drivers(2.5V/3.3V 20位緩沖器/驅(qū)動(dòng)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 20位緩沖器/驅(qū)動(dòng)器（2.5V/3.3V的20位緩沖器/驅(qū)動(dòng)器（三態(tài)輸出）） |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大小： | 197K |
| 代理商： | SN54ALVTH162827 |
SN54ALVTH162827, SN74ALVTH162827
2.5-V/3.3-V 20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES079A – JULY 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
Output Ports Have Equivalent 30-
Series
Resistors, So No External Resistors Are
Required
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Capability (–12 mA/12 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH162827 are 20-bit buffers/line drivers
designed for low-voltage 2.5-V or 3.3-V V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
The ’ALVTH162827 are composed of two 10-bit
sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1 and
1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
All outputs are designed to sink up to 12 mA and include 30-
resistors to reduce overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVTH162827 is available in TI’s thin very small-outline package (DGV), which provides the same
I/O pin count and functionality of standard Widebus packages in less than half the printed circuit board area.
The SN54ALVTH162827 is characterized for operation over the full military temperature range of –55
°
C to
125
°
C. The SN74ALVTH162827 is characterized for operation from –40
°
C to 85
°
C.
Copyright
1996, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1OE2
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
SN54ALVTH162827 . . . WD PACKAGE
SN74ALVTH162827 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
Widebus is a trademark of Texas Instruments Incorporated.
P
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| SN54ALVTH16373WD | 800mA, 3.3V Output, Low Dropout Voltage Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 |
| SN74ALVTH16373DGG | 2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS |
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