參數(shù)資料
型號： SN54ALVTH16373
廠商： Texas Instruments, Inc.
英文描述： 2.5-V/3.3-V 16-Bit D-Latches With 3-State Outputs(2.5V/3.3V 16位D鎖存器(三態(tài)輸出))
中文描述： 2.5-V/3.3-V 16位D鎖存器與三態(tài)輸出（2.5V/3.3V的16位?鎖存器（三態(tài)輸出））
文件頁數(shù)： 1/9頁
文件大?。?/td> 205K
代理商： SN54ALVTH16373
SN54ALVTH16373, SN74ALVTH16373
2.5-V/3.3-V 16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCES067A – JUNE 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Capability (–32 mA/64 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16373 are 16-bit transparent D-type
latches with 3-state outputs designed for 2.5-V or
3.3-V V
CC
operation, but with the capability to
provide a TTL interface to a 5-V system
environment. These devices are particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up
at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54ALVTH16373 . . . WD PACKAGE
SN74ALVTH16373 . . . DGG, DGV, OR DL PACKAGE
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1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
P
相關(guān)PDF資料
PDF描述
SN54ALVTH16374WD 800mA, 5.0V Output, Low Dropout Voltage Regulator; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98
SN54ALVTH16374 2.5-V/3.3-V 16-Bit Edge-Triggered D-Type Flip-Flops With 3-State Outputs(2.5V/3.3V 16位邊沿D觸發(fā)器(三態(tài)輸出))
SN54ALVTH16500 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V 18位通用總線收發(fā)器(三態(tài)輸出))
SN74ALVTH16500 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V18位通用總線收發(fā)器(三態(tài)輸出))
SN54ALVTH16501 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V 18位通用總線收發(fā)器(三態(tài)輸出))
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