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參數(shù)資料
| 型號： | SN54ALVTH16500 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V 18位通用總線收發(fā)器(三態(tài)輸出)) |
| 中文描述： | 2.5-V/3.3-V 18位通用總線收發(fā)器與三態(tài)輸出（2.5V/3.3V的18位通用總線收發(fā)器（三態(tài)輸出）） |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 243K |
| 代理商： | SN54ALVTH16500 |
SN54ALVTH16500, SN74ALVTH16500
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCES069A – JUNE 1996 – REVISED JULY 1996
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Members of the Texas Instruments
Widebus
Family
High-Impedance State During Power Up
and Power Down
5-V I/O Compatible
High-Drive Outputs (–32 mA/64 mA)
Typical V
OLP
(Output Ground Bounce)
< 0.8 V at V
CC
= 3.3 V, T
A
= 25
°
C
Auto 3-State Eliminates Bus Current
Loading When Voltage at the Output
Exceeds V
CC
Bus-Hold Data Inputs Eliminate the Need
for External Pullup/Pulldown Resistors
Power Off Disables Inputs/Outputs,
Permitting Live Insertion
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
description
The ’ALVTH16500 are 18-bit universal bus
transceivers designed for 2.5-V or 3.3-V V
CC
operation, but with the capability to provide a TTL
interface to a 5-V system environment.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active
high. When OEAB is high, the B-port outputs are active. When OEAB is low, the B-port outputs are in the
high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 1.2 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE should be tied to V
CC
through a pullup resistor
and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by
the current-sinking/current-sourcing capability of the driver.
Copyright
1996, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN54ALVTH16500 . . . WD PACKAGE
SN74ALVTH16500 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SN74ALVTH16500 | 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V18位通用總線收發(fā)器(三態(tài)輸出)) |
| SN54ALVTH16501 | 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V 18位通用總線收發(fā)器(三態(tài)輸出)) |
| SN74ALVTH16501 | 2.5-V/3.3-V 18-Bit Universal Bus Transceivers With 3-State Outputs( 2.5V/3.3V18位通用總線收發(fā)器(三態(tài)輸出)) |
| SN54ALVTH16543 | 2.5-V/3.3-V 16-Bit Registered Transceivers( 2.5V/3.3V 16位記錄收發(fā)器(三態(tài)輸出)) |
| SN74ALVTH16543 | 2.5-V/3.3-V 16-Bit Registered Transceivers(2.5V/3.3V16位記錄收發(fā)器) |
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