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SM320C6201, SMJ320C6201B
DIGITAL SIGNAL PROCESSORS
SGUS028A – NOVEMBER 1998 – REVISED JANUARY 1999
70
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
DMAC, TIMER, POWER-DOWN TIMING (CONTINUED)
switching characteristics for power-down outputs (see Figure 40)
NO.
PARAMETER
’C6201-150
’C6201B-150
’C6201B-200
UNIT
MIN
2*
MAX
MIN
MAX
1
td(CKO1H-PDV)
Delay time, CLKOUT1 high to PD valid
5
3
5
ns
*This parameter is not production tested.
1
1
CLKOUT1
PD
Figure 40. Power-Down Timing
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design phase of development. Characteristic data and other
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change or discontinue these products without notice.