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參數(shù)資料
| 型號： | SMJ320C31KGDM40B |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 32-BIT, 40 MHz, OTHER DSP, UUC132 |
| 封裝： | DIE |
| 文件頁數(shù)： | 39/59頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | SMJ320C31KGDM40B |
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SMJ320C31, SMJ320LC31, SMQ320LC31
DIGITAL SIGNAL PROCESSORS
SGUS026G APRIL 1998 REVISED SEPTEMBER 2006
44
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing requirements for the timer pin.
timing for timer pin (see Figure 32 and Note 7)
NO.
’C31-40,
’LC31-40
’C31-50
’C31-60
UNIT
MIN
MAX
MIN
MAX
88
tsu(TCLK-H1L)
Setup time, TCLK external
before H1 low
10
6
ns
89
th(H1L-TCLK)
Hold time, TCLK external after
H1 low
0
ns
90
td(H1H-TCLK)
Delay time, H1 high to TCLK
internal valid
9
8
ns
91
tc(TCLK)
Cycle time, TCLK
TCLK ext
tc(H)×2.6
ns
91
tc(TCLK)
Cycle time, TCLK
TCLK int
tc(H)×2
tc(H)×232*
tc(H)×2
tc(H)×232*
ns
92
tw(TCLK)
Pulse duration,
TCLK ext
tc(H)+10
ns
92
tw(TCLK)
Pulse duration,
TCLK high/low
TCLK int
[tc(TCLK)/2]5 [tc(TCLK)/2]+5
ns
NOTE 7: Numbers 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
90
89
Peripheral
Pin
(see Note A)
H1
H3
88
91
92
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 32. Timing for Timer Pin
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