參數(shù)資料
型號(hào): SI5374B-A-GL
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PBGA80
封裝: 10 X 10 MM, ROHS COMPLIANT, PLASTIC, MO-192, BGA-80
文件頁數(shù): 52/64頁
文件大?。?/td> 303K
代理商: SI5374B-A-GL
Si5374
56
Preliminary Rev. 0.4
D1
A6
F9
J4
CS_CA_A
CS_CA_B
CS_CA_C
CS_CA_D
I/O
LVCMOS DSPLLq Input Clock Select/Active Clock Indicator.
Input
: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates. If configured for input, must be
tied high or low.
Output
: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active clock. If
alarms exist on both clocks, CK_ACTV will indicate the last active
clock that was used before entering the digital hold state. The
CK_ACTV_PIN
register bit must be set to 1 to reflect the active
clock status to the CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
G5
SCL
I
LVCMOS I2C Serial Clock.
This pin functions as the serial clock input.
This pin has a weak pull-down.
G6
SDA
I/O
LVCMOS I2C Serial Data.
I2C pin functions as the bi-directional serial data port.
Table 9. Si5374 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal
Level
Description
Note:
Internal register names are indicated by italics, e.g., IRQ_PIN. See Si5374 Register Map.
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Si5374-EVB 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 QUAD DSPLL 8IN/8OUT CLOCK EVAL KIT RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V
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