參數(shù)資料
型號(hào): SI5356AAXXXXXGM
廠商: SILICON LABORATORIES
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
封裝: 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24
文件頁數(shù): 6/26頁
文件大?。?/td> 345K
代理商: SI5356AAXXXXXGM
Si5356
14
Preliminary Rev. 0.3
3.10. I2C Interface
The Si5356 control interface is a 2-wire bus for
bidirectional communication. The bus consists of a
bidirectional serial data line (SDA) and a serial clock
input (SCL). The device operates as a slave device on
the 2-wire bus and is compatible with I2C specifications.
Both lines must be connected to the positive supply via
an external pull-up. Standard-Mode (100 kbps) and
Fast-Mode (400 kbps) operation and 7-bit addressing
are supported as specified in the I2C-Bus Specification
standard. To accommodate multiple Si5356 devices on
the same I2C bus, the Si5356 has pin 3 as I2C_LSB.
The complete 7-bit I2C bus address for the device is
70h or 71h depending upon the state of the I2C_LSB
pin. In binary, this is written as 111 000[I2C_LSB]. See
Figure 8 for the command format for both read and write
access.
Data is always sent MSB first. Table 7 includes the AC
and DC electrical parameters for the SCL and SDA I/
Os, respectively. The timing specifications and timing
diagram for the I2C bus can be found in the I2C-Bus
Specification standard. SDA timeout support is
supported for compatibility with SMBus interfaces.
The I2C interface is 3.3 V tolerant.
The I2C bus can be operated at a bus voltage of 1.71 to
3.63 V and should have a pullup resistor as
recommended by the I2C-Bus Specification.
Figure 7. Status Register
Figure 8. I2C/SMBus-Compatible Command Format
218
0
1
2
3
4
5
6
7
LOS
XTAL
LOS
Clk
SYS
Cal
LOL
System Calibration
(Lock Acquisition)
Loss of Signal
XTAL Input
Loss of Signal
Clock Input
Loss of Lock
From master to slave
From slave to master
1 – Read
0 – Write
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
Repeated Start Read
Write
A
Reg Addr [7:0]
A
S Slv Addr [6:0]
0
S
Slv Addr [6:0] 1 A
A
Data [7:0]
N P
Data [7:0]
A
Reg Addr [7:0]
A
S Slv Addr [6:0]
0
A
Data [7:0]
P
Read Data
A
Data [7:0]
A
S Slv Addr [6:0]
1
N P
Data [7:0]
Write Data
A
Reg Addr [7:0]
A
S Slv Addr [6:0]
0
P
Two Command Read
Optional
相關(guān)PDF資料
PDF描述
SI5356A-AXXXXX-GMR 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24
SI5369B-C-GQR 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
SI5369B-C-GQ 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
SI5369C-C-GQ 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100
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