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參數(shù)資料
| 型號(hào)： | SI5356AAXXXXXGM |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 4/26頁 |
| 文件大?。?/td> | 345K |
| 代理商： | SI5356AAXXXXXGM |
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Si5356
12
Preliminary Rev. 0.3
When creating a custom RAM configuration, use the
following procedure:
1. Create a device configuration (register map) using
ClockBuilder Desktop (v2.7 or later; see "3.1.1.
manually using the equations in “AN565: Configuring
the Si5356A”.
a. Configure the frequency plan.
b. Configure the output driver format and supply
voltage.
c. Configure initial phase offset (if desired).
d. Configure spread spectrum (if desired).
2. Save the configuration using the Options > Save
Register Map File or Options > Save C code Header
File, or create the register contents by the
conversions listed in AN565.
At this point, the new configuration can be written to the
device RAM according to the instructions in “3.5.3.
3.5.3. Writing a Custom Configuration to RAM
Writing a new configuration (register map) to the RAM
consists of pausing the LOL state-machine, writing new
values to the IC accounting for the write-allowed mask
given in AN565, validating the input clock or crystal,
locking the PLL to the input with the new configuration,
restarting the LOL state-machine, and calibrating the
VCO for robust operation across temperature. The flow
chart in Figure 5 on page 12 enumerates the details:
Note:
The write-allowed mask specifies which bits must be
read and modified before writing the entire register
byte (a.k.a. read-modify-write). “AN428: Jump Start: In-
System, Flash-Based Programming for Silicon Labs’
Timing Products” illustrates the procedure defined in
Section 3.5.2 with ANSI C code.
3.5.4. Modifying a MultiSynth Output Divider Ratio/
Frequency Configuration
Any of the four output frequencies of a previously
configured Si5356 may be modified without disturbing
the other outputs. In this case, do not write the feedback
Multisynth registers. Instead, only write the set of
registers associated with the output MultiSynth divider
of interest (see “AN565: Configuring the Si5356A”).
To avoid intermediate frequencies, it is recommended
that the output to be modified is disabled before
changing the divider ratios (see AN565 for a description
of Register 230).
Any output Multisynth that is reconfigured will lose its
output skew alignment with the other outputs.
SOFT_RESET can be used to realign the outputs;
however, a soft reset will temporarily disable all outputs
in the process of realignment.
3.5.5. Writing a Custom Configuration to NVM
An alternative to ordering an Si5356 with a custom NVM
configuration is to use the field programming kit
(Si5338/56-PROG-EVB) to write directly to the NVM of
a "blank" Si5356. Since NVM is an OTP memory, it can
only be written once. The default configuration can be
reconfigured by writing to RAM through the I2C interface
3.6. Output Phase Adjustment
The Si5356 has a digitally-controlled phase adjustment
feature that allows the user to adjust the phase of each
output clock in relation to the other output clocks. The
phase of each output clock can be adjusted with an
error of <20 ps over a range of ±45 ns. This feature is
available on any clock output that does not have Spread
Spectrum enabled.
Figure 5. I2C Programming Procedure
Re giste r
Map
Use Clo ckB u ild er
D e skto p v3 .0 or la te r
S et re g2 41 = 0x65
W rite n ew con fig uration to de vice
acco un tin g fo r the w rite-a llow e d m a sk
(S ee A N 565 : C o nfigurin g the S i53 56 A )
D isa ble O u tp uts
S e t O E B _ A L L = 1; reg230[4]
E n ab le O u tp uts
S e t O E B _A LL = 0; re g2 30 [4 ]
A pp ly S o ft R eset
S et S O F T _ R E S E T = 1; re g2 46 [1 ]
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5356A-AXXXXX-GMR | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| SI5369B-C-GQR | 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369B-C-GQ | 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369C-C-GQ | 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369D-C-GQ | 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5356A-Axxxxx-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-programmable CMOS clock generator, 1 - 200 MHz, Custom Factory Programmed NVM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5356A-B-GM | 功能描述:時(shí)鐘緩沖器 I2C-prog 8-out CMOS Clk gen 1-200MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| Si5356A-B-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C CMOS Clk Gen 1-200MHz Blank NVM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5356A-BXXXXX-GM | 制造商:Silicon Laboratories Inc 功能描述:IC CLK GENERATOR I2C 24QFN |
| Si5356-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Si5356 Eval Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
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