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參數(shù)資料
| 型號： | SI5356AAXXXXXGM |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 5/26頁 |
| 文件大?。?/td> | 345K |
| 代理商： | SI5356AAXXXXXGM |
Si5356
Preliminary Rev. 0.3
13
3.7. CMOS Output Drivers
The Si5356 has 4 banks of outputs with each bank
comprised of 2 clocks for a total of 8 CMOS outputs per
device. By default, each bank of CMOS output clocks
are in-phase. Alternatively, each output clock can be
inverted. This feature enables each output pair to
operate as a differential CMOS clock. Each of the
output banks can operate from a different VDDO supply
(1.8 V, 2.5 V, 3.3 V), simplifying usage in mixed supply
applications. All clock outputs between 5 and 200 MHz
are in-phase to within ±150 ps.
The CMOS output driver has a controlled impedance in
the range of 42 to 50
which includes an internal 22
series resistor. An external series resistor is not needed
when driving 50
traces. If higher impedance traces
are used then a series resistor may be added. A typical
configuration is shown in Figure 6.
3.8. Jitter Performance
The Si5356 provides consistently low jitter for any
combination
of
output
frequencies.
The
device
leverages a low phase noise single PLL architecture
and Silicon Laboratories’ patented MultiSynth fractional
output divider technology to deliver period jitter less
than
100 ps
pk-pk
(max)
for
any
frequency
configuration. This level of jitter performance is
guaranteed across process, temperature and voltage.
The Si5356 provides superior performance to traditional
multi-PLL solutions which may suffer from degraded
jitter performance depending on frequency plan and the
number of active PLLs.
3.9. Status Indicators
An interrupt pin (INTR) is available to indicate a loss of
signal (LOS) condition, a PLL loss of lock (LOL)
condition, or that the PLL is in the process of acquiring
lock (SYS_CAL). As shown in Figure 7, a status register
at address 218 is available to help identify the exact
event that caused the interrupt pin to become active. A
LOS condition occurs when there is no clock input to the
Si5356. The loss of lock algorithm works by
continuously monitoring the frequency difference
between the two inputs of the phase frequency detector.
When this frequency difference is greater than
1000 ppm, a loss of lock condition is declared. Note that
the VCO will track the input clock frequency for up to
~25000 ppm, which will keep the inputs to the phase
frequency detector at the same frequency until the PLL
comes out of lock. When a clock input is removed, the
interrupt pin will assert, and the clock outputs may drift
up to 5%. When the input clock is reapplied with an
appropriate frequency, the PLL will again lock.
Figure 6. CMOS Output Driver Configuration
MultiSynth
Bank A
+1.8V, +2.5V, +3.3V
VDDOA
CLK0
CLK1
MultiSynth
Bank C
+1.8V, +2.5V, +3.3V
VDDOC
CLK4
CLK5
MultiSynth
Bank D
+1.8V, +2.5V, +3.3V
VDDOD
CLK6
CLK7
MultiSynth
Bank B
+1.8V, +2.5V, +3.3V
VDDOB
CLK2
CLK3
PLL
50
Si5356
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5356A-AXXXXX-GMR | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| SI5369B-C-GQR | 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369B-C-GQ | 808 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369C-C-GQ | 346 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
| SI5369D-C-GQ | 243 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5356A-Axxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-programmable CMOS clock generator, 1 - 200 MHz, Custom Factory Programmed NVM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5356A-B-GM | 功能描述:時鐘緩沖器 I2C-prog 8-out CMOS Clk gen 1-200MHz RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| Si5356A-B-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C CMOS Clk Gen 1-200MHz Blank NVM RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5356A-BXXXXX-GM | 制造商:Silicon Laboratories Inc 功能描述:IC CLK GENERATOR I2C 24QFN |
| Si5356-EVB | 功能描述:時鐘和定時器開發(fā)工具 Si5356 Eval Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
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