參數(shù)資料
型號: SI5327D-C-GMR
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 243 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC36
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
文件頁數(shù): 44/60頁
文件大?。?/td> 715K
代理商: SI5327D-C-GMR
Si5327
Preliminary Rev. 0.4
49
7. Pin Descriptions: Si5327
Pin #
Pin Name
I/O
Signal Level
Description
1
RST
ILVCMOS
External Reset.
Active low input that performs external hardware reset of device.
Resets all internal logic to a known state and forces the device reg-
isters to their default value. Clock outputs are tristated during reset.
The part must be programmed after a reset or power on to get a
clock output. See the Si53xx Family Reference Manual for details.
This pin has a weak pull-up.
2, 9, 14,
19, 20, 30,
33
NC
No Connection.
Leave floating. Make no external connections to this pin for normal
operation.
3
INT_LOS1
O
LVCMOS
Interrupt/CKIN1 LOS Indicator.
This pin functions as a device interrupt output or an alarm output for
CKIN1. If used as an interrupt output, INT_PIN must be set to 1. The
pin functions as a maskable interrupt output with active polarity con-
trolled by the INT_POL register bit.
If used as an alarm output, the pin functions as a LOS alarm indica-
tor for CKIN1. Set CK1_BAD_PIN = 1 and INT_PIN =0.
0 = CKIN1 present
1 = LOS on CKIN1
The active polarity is controlled by CK_BAD_POL. If no function is
selected, the pin tristates.
Note:
Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”.
1
2
3
29
30
31
32
33
34
35
36
20
21
22
23
24
25
26
27
10 11 12 13 14 15 16 17
4
5
6
7
8
NC
RST
LOS2
INT_LOS1
GND
VDD
XA
VD
D
RA
TE
CK
IN2+
CK
IN
2–
NC
GN
D
CK
IN1+
CK
IN
1–
CKSEL
SCL
SDA_SDO
A1
A2_SS
SDI
CK
OU
T
1
NC
GN
D
VD
D
NC
CK
OUT
2–
CK
OUT
2+
CMO
D
E
GND
Pad
A0
NC
9
18
19
28
XB
LOL
NC
CK
O
U
T
1
+
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