參數(shù)資料
型號: SI5327D-C-GMR
廠商: SILICON LABORATORIES
元件分類: 時鐘產(chǎn)生/分配
英文描述: 243 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC36
封裝: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD, QFN-36
文件頁數(shù): 3/60頁
文件大?。?/td> 715K
代理商: SI5327D-C-GMR
Si5327
Preliminary Rev. 0.4
11
Table 4. AC Specifications
(VDD = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Single-Ended Reference Clock Input Pin XA (XB with cap to GND)
Input Resistance
XARIN
RATE = M,
ac coupled
—12
k
Input Voltage Swing
XAVPP
RATE = M,
ac coupled
0.5
1.2
VPP
Differential Reference Clock Input Pins (XA/XB)
Input Voltage Swing
XA/XBVPP
RATE = M
0.5
2.4
VPP
CKINn Input Pins
Input Frequency
CKNF
0.002
710
MHz
Input Duty Cycle
(Minimum Pulse
Width)
CKNDC
Whichever is smaller
(i.e., the 40% / 60%
limitation applies only
to high frequency
clocks)
40
60
%
2—
ns
Input Capacitance
CKNCIN
——
3
pF
Input Rise/Fall Time
CKNTRF
20–80%
——
11
ns
CKOUTn Output Pins
Output Frequency
(Output not config-
ured for CMOS or
Disabled)
CKOF
N1_HS
6
0.002
808
MHz
Maximum Output
Frequency in CMOS
Format
CKOF
212.5
MHz
Output Rise/Fall
(20–80 %) @
622.08 MHz output
CKOTRF
Output not configured for
CMOS or Disabled
—230
350
ps
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =1.71
CLOAD =5 pF
——
8
ns
Output Rise/Fall
(20–80%) @
212.5 MHz output
CKOTRF
CMOS Output
VDD =2.97
CLOAD =5 pF
——
2
ns
*Note:
Input to output phase skew after an ICAL is not controlled and can assume any value.
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