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參數(shù)資料
| 型號(hào)： | SI5020-B-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DATA REC SONET/SDH 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 75 |
| 系列： | SiPHY™, DSPLL® |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，ATM 應(yīng)用 |
| 輸入： | 時(shí)鐘 |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.7GHz |
| 電源電壓： | 2.375 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN（4x4） |
| 包裝： | 管件 |
Si5020
Rev. 1.5
13
Figure 5. Jitter Transfer Specification
4.8. Powerdown
The Si5020 provides a powerdown pin, PWRDN/CAL,
that disables the output drivers (DOUT, CLKOUT).
When the PWRDN/CAL pin is driven high, the positive
and negative terminals of CLKOUT and DOUT are each
tied to VDD through 100
on-chip resistors. This
feature is useful in reducing power consumption in
applications that employ redundant serial channels.
When PWRDN/CAL is released (set to low) the digital
logic resets to a known initial condition, recalibrates the
DSPLL, and will begin to lock to the data stream.
4.9. Device Grounding
The Si5020 uses the GND pad on the bottom of the 20-
pin micro leaded package (MLP) for device ground. This
pad should be connected directly to the analog supply
ground. See Figures 10 and 11 for the ground (GND)
pad location.
4.10. Bias Generation Circuitry
The Si5020 makes use of an external resistor to set
internal bias currents. The external resistor allows
precise generation of bias currents, which significantly
reduces
power
consumption
versus
traditional
implementations that use an internal resistor. The bias
generation circuitry requires a 10 k
(1%) resistor
connected between REXT and GND.
4.11. Differential Input Circuitry
The Si5020 provides differential inputs for both the high-
speed data (DIN) and the reference clock (REFCLK)
inputs. An example termination for these inputs is
shown in Figure 6. In applications where direct dc
coupling is possible, the 0.1
F capacitors may be
omitted. The DIN and REFCLK input amplifiers require
an input signal with a minimum differential peak-to-peak
voltage listed in Table 2 on page 6.
Figure 6. Input Termination for DIN and REFCLK (AC Coupled)
0.1 dB
Jitter
Trans f er
Fc
Frequenc y
20 dB/Dec ade
Slope
Fc
(k Hz )
SONET
Data Rate
OC-48
OC-12
OC-3
2000
500
130
A c c eptable
Range
Dif f erential Driv er
Si5020
0.1 F
Zo = 50
RF C LK +
RF C LK –
2.5 k
10 k
102
VDD
GND
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5020-B-GMR | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 Multi-Rate SONET SDH CDR RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020-BM | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020-BMR | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 SNT/SDH GbE 2.7Gbps OC48/12/3 STM16/4/1 RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| SI5020C-BA | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi-Rate SONET/ SDH CDR Morph Board RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5020C-BAR | 制造商:Silicon Laboratories Inc 功能描述: |
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